AD7988-1 Analog Devices, AD7988-1 Datasheet - Page 14

• Manufacturer Part Number: AD7988-1
• Description: 16-Bit, 100ksps, Ultra Low Power 16-Bit SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7988-1

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,5V p-p,Uni (Vref),Uni 5.0V
• Pkg Type: SOP

AD7988-1/AD7988-5
THEORY OF OPERATION
CIRCUIT INFORMATION
The
supply, precise 16-bit ADCs that use a successive approximation
architecture.
The
second (100 kSPS), whereas the
throughput of 500 kSPS, and they power down between
conversions. When operating at 10 kSPS, for example, the
ADC consumes 70 µW typically, ideal for battery-powered
applications.
The
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The
family. It is housed in a 10-lead MSOP or a tiny 10-lead LFCSP
(QFN) that combines space savings and allows flexible
configurations.
CONVERTER OPERATION
The
charge redistribution DAC. Figure 29 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
AD7988-1/AD7988-5
AD7988-1
AD7988-x
AD7988-x
AD7988-x
GND
is capable of converting 100,000 samples per
provides the user with on-chip track-and-hold
can be interfaced to any 1.8 V to 5 V digital logic
is a successive approximation ADC based on a
REF
IN+
IN–
devices are fast, low power, single-
32,768C
32,768C
AD7988-5
16,384C
16,384C
MSB
MSB
is capable of a
4C
4C
Figure 29. ADC Simplified Schematic
2C
2C
Rev. A | Page 14 of 24
C
C
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is completed and the CNV input goes high, a
conversion phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the GND input.
Therefore, the differential voltage between the IN+ and IN−
inputs captured at the end of the acquisition phase are applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (V
control logic toggles these switches, starting with the MSB, to
bring the comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition phase
and the control logic generates the ADC output code.
Because the
serial clock, SCK, is not required for the conversion process.
C
C
LSB
LSB
SW+
SW–
AD7988-x
SWITCHES CONTROL
COMP
has an on-board conversion clock, the
CONTROL
REF
LOGIC
CNV
/2, V
REF
BUSY
OUTPUT CODE
/4 … V
REF
/65,536). The
Data Sheet