AD7988-1 Analog Devices, AD7988-1 Datasheet - Page 20

• Manufacturer Part Number: AD7988-1
• Description: 16-Bit, 100ksps, Ultra Low Power 16-Bit SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7988-1

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,5V p-p,Uni (Vref),Uni 5.0V
• Pkg Type: SOP

AD7988-1/AD7988-5
CHAIN MODE
This mode can be used to daisy-chain multiple
devices on a 3-wire serial interface. This feature is useful for
reducing component count and wiring connections, for example,
in isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two
shown in Figure 38, and the corresponding timing is given in
Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion and selects the chain
mode. In this mode, CNV is held high during the conversion
ACQUISITION
SDO
SDI
A
= SDI
SDO
t
A
CNV
SCK
HSCKCNV
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
SDI
t
EN
AD7988-1/
AD7988-5
CNV
SCK
A
t
HSDO
D
D
AD7988-x
A
B
15
15
1
SDO
t
AD7988-x
SSDISCK
D
D
Figure 39. Chain Mode Serial Interface Timing
Figure 38. Chain Mode Connection Diagram
2
A
B
14
14
t
devices is
DSDO
D
D
3
A
B
13
13
Rev. A | Page 20 of 24
t
SCKL
SDI
t
HSDISCK
14
AD7988-1/
AD7988-5
t
D
D
CNV
SCK
15
CYC
phase and the subsequent data readback. When the conversion
is complete, the MSB is output onto SDO and the
enters the acquisition phase and powers down. The remaining
data bits stored in the internal shift register are clocked by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 16 × N clocks are required to read back the N ADCs. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate and, consequently, more
AD7988-x
has an acceptable hold time. The maximum conversion rate
may be reduced due to the total readback time.
A
B
B
1
1
ACQUISITION
t
SCK
t
t
SCKH
D
D
16
ACQ
A
B
0
0
SDO
devices in the chain, provided that the digital host
D
17
A
15
D
18
A
14
CONVERT
DATA IN
CLK
DIGITAL HOST
30
D
31
A
1
D
32
A
0
Data Sheet
AD7988-x