AD9257

Manufacturer Part NumberAD9257
DescriptionOctal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
ManufacturerAnalog Devices
AD9257 datasheet
 


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Data Sheet
FEATURES
Low power: 55 mW per channel at 65 MSPS with scalable
power options
SNR = 75.5 dB (to Nyquist)
SFDR = 91.6 dBc (to Nyquist)
DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
GENERAL DESCRIPTION
The
AD9257
is an octal, 14-bit, 40 MSPS and 65 MSPS analog-
to-digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Octal, 14-Bit, 40/65 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9257
VIN+ A
VIN– A
VIN+ B
VIN– B
VIN+ C
VIN– C
VIN+ D
VIN– D
VIN+ E
VIN– E
VIN+ F
VIN– F
VIN+ G
VIN– G
VIN+ H
VIN– H
VREF
SENSE
VCM
REF
SELECT
SYNC
RBIAS
AGND
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The
AD9257
is available in an RoHS-compliant, 64-lead LFCSP.
It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2.
Low Power of 55 mW/Channel at 65 MSPS with Scalable
Power Options.
3.
Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 455 MHz and supports
double data rate (DDR) operation.
4.
User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5.
Pin Compatible with the
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9257
PDWN
DRVDD
14
D+ A
SERIAL
ADC
D– A
LVDS
14
D+ B
SERIAL
ADC
D– B
LVDS
14
D+ C
SERIAL
ADC
D– C
LVDS
14
D+ D
SERIAL
ADC
D– D
LVDS
14
D+ E
SERIAL
ADC
D– E
LVDS
14
D+ F
SERIAL
ADC
D– F
LVDS
14
D+ G
SERIAL
ADC
D– G
LVDS
14
D+ H
SERIAL
ADC
D– H
LVDS
FCO+
1.0V
DATA
FCO–
RATE
SERIAL PORT
DCO+
MULTIPLIER
INTERFACE
DCO–
CSB
SDIO/
SCLK/
CLK+ CLK–
DFS
DTP
Figure 1.
AD9637
(12-Bit Octal ADC).
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.

AD9257 Summary of contents

  • Page 1

    ... User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. 5. Pin Compatible with the One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9257 PDWN DRVDD SERIAL ADC D– A LVDS ...

  • Page 2

    ... Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Specifications .................................................................. 6 Absolute Maximum Ratings ............................................................ 8 Thermal Characteristics .............................................................. 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 AD9257-65 .................................................................................. 11 AD9257-40 .................................................................................. 14 Equivalent Circuits ......................................................................... 17 Theory of Operation ...................................................................... 18 Analog Input Considerations .................................................... 18 Voltage Reference ....................................................................... 19 REVISION HISTORY 10/11—Revision 0: Initial Version   Clock Input Considerations ...................................................... 20   ...

  • Page 3

    ... Full 3.5 Full 1.7 1.8 1.9 Full 1.7 1.8 1.9 Full 147 156 Full 53 85 25°C 38 Full 360 434 25°C 333 25°C 1 25°C 74 Rev Page AD9257 AD9257-65 Min Typ Max Unit 14 Bits Guaranteed −0.7 −0.3 +0.1 % FSR 0 0.23 0.6 % FSR −6.0 −2.9 +1.0 % FSR −1.0 +1.6 +5.0 % FSR −1.0 ±0.6 +1.6 LSB −4.0 ± ...

  • Page 4

    ... Full −99 −86 25°C −99 25°C 25°C −98 25°C 25°C 95 25°C Rev Page Data Sheet AD9257-65 Min Typ Max Unit 75.7 dBFS 73.3 75.6 dBFS 75.5 dBFS 74.9 dBFS dBFS 73.2 dBFS 74.7 dBFS 72.0 74.6 dBFS 74.4 dBFS 73 ...

  • Page 5

    ... Full 1.79 Full LVDS Full 247 350 Full 1.13 1.21 Twos complement LVDS Full 150 200 Full 1.13 1.21 Twos complement Rev Page AD9257 AD9257-65 Min Typ Max Unit −98 dB −94 dB 650 MHz Max Unit 3.6 V p-p AVDD + 0 kΩ pF AVDD + 0.2 V 0.8 V kΩ pF AVDD + 0 ...

  • Page 6

    ... AD9257 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. 1 Parameter , 2 3 CLOCK Input Clock Rate Conversion Rate Clock Pulse Width High ( Clock Pulse Width Low ( OUTPUT PARAMETERS Propagation Delay ( ...

  • Page 7

    ... MSB N – – – – – – – – MSB N – – – – – – – 16 AD9257 D12 N – 16 D10 N – 16 ...

  • Page 8

    ... AD9257 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs (D± x, DCO+, DCO−, FCO+, FCO−) to AGND CLK+, CLK− to AGND VIN+ x, VIN− AGND SCLK/DTP, SDIO/DFS, CSB to AGND SYNC, PDWN to AGND RBIAS to AGND VREF, SENSE to AGND ...

  • Page 9

    ... Power-Down. ADC A Analog Input True, ADC A Analog Input Complement. ADC B Analog Input Complement, ADC B Analog Input True. ADC C Analog Input True, ADC C Analog Input Complement. ADC D Analog Input Complement, ADC D Analog Input True. Rev Page AD9257 48 AVDD 47 VIN VIN– B ...

  • Page 10

    ... AD9257 Pin No. Mnemonic 54 RBIAS 55 SENSE 56 VREF 57 VCM 58 SYNC 60, 61 VIN+ E, VIN− E 63, 64 VIN− F, VIN+ F Description Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Reference Mode Selection. Voltage Reference Input/Output. Analog Output Voltage at Midsupply. Sets common mode of the analog inputs. ...

  • Page 11

    ... FREQUENCY (MHz) = 30.5 MHz 65MSPS 123.4MHz AT –1dBFS –15 SNR = 72.2dB (73.2dBFS) SFDR = 83.0dBc –30 –45 –60 –75 –90 –105 –120 –135 FREQUENCY (MHz) = 123.4 MHz AD9257 MSPS SAMPLE MSPS SAMPLE MSPS SAMPLE ...

  • Page 12

    ... AD9257 0 –20 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90 –78 –66 –54 –42 INPUT AMPLITUDE (dBFS) Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with MHz and MHz, f IN1 IN2 SAMPLE 120 SFDRFS 100 ...

  • Page 13

    ... Figure 18. Input-Referred Noise Histogram, f 2.0 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 OUTPUT CODE Figure 19. INL 9.7 MHz SAMPLE 0.936 LSB RMS –0.2 –0.4 –0.6 –0.8 –1 MSPS SAMPLE = 65 MSPS Rev Page 1.0 0.8 0.6 0.4 0.2 0 OUTPUT CODE Figure 20. DNL 9.7 MHz MSPS IN SAMPLE AD9257 ...

  • Page 14

    ... AD9257 AD9257-40 0 40MSPS –15 9.7MHz AT –1dBFS SNR = 74.8dB (75.8dBFS) SFDR = 96.9dBc –30 –45 –60 –75 –90 –105 –120 –135 FREQUENCY (MHz) Figure 21. Single-Tone 16k FFT with f = 9.7 MHz 40MSPS –15 30.5MHz AT –1dBFS SNR = 74.6dB (75.6dBFS) SFDR = 98.8dBc –30 – ...

  • Page 15

    ... SFDR SNRFS SAMPLE FREQUENCY (MSPS) Figure 31. SNR/SFDR vs. Encode 30.5 MHz IN 500,000 450,000 400,000 350,000 300,000 250,000 200,000 150,000 100,000 50,000 0 OUTPUT CODE Figure 32. Input-Referred Noise Histogram, f SAMPLE AD9257 160 180 200 35 40 0.846 LSB RMS = 40 MSPS ...

  • Page 16

    ... AD9257 2.0 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 OUTPUT CODE Figure 33. INL 9.7 MHz SAMPLE –0.2 –0.4 –0.6 –0.8 –1 MSPS Rev Page Data Sheet 1.0 0.8 0.6 0.4 0.2 0 OUTPUT CODE Figure 34. DNL 9.7 MHz MSPS IN SAMPLE ...

  • Page 17

    ... AVDD 350Ω SCLK/DTP, SYNC, AND PDWN 30kΩ AVDD 375Ω RBIAS AND VCM Figure 40. Equivalent RBIAS, VCM Circuit AVDD 30kΩ 350Ω CSB Figure 41. Equivalent CSB Input Circuit AVDD 375Ω VREF 7.5kΩ Figure 42. Equivalent VREF Circuit AD9257 ...

  • Page 18

    ... VCM pin. The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9257, the largest input span available p-p. 100 ...

  • Page 19

    ... AD9257 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9257. VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that follow. The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μ ...

  • Page 20

    ... Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz) Drift CLOCK INPUT Rev Page AD9257 has a very flexible clock input structure. The clock AD9257 (at clock rates 520 MHz prior to the AD9257 ® Mini-Circuits ADT1-1WT, 1:1 Z 0.1µF 0.1µF XFMR 100Ω 50Ω 0.1µF SCHOTTKY 0.1µ ...

  • Page 21

    ... This allows the user to provide a wide range of clock input duty cycles without affecting the per- formance of the AD9257. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on. Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit ...

  • Page 22

    ... Figure 55). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9257. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...

  • Page 23

    ... Figure 58. FCO 500mV/DIV DCO 500mV/DIV DATA 500mV/DIV Figure 57. LVDS Output Timing Example in ANSI-644 Mode (Default) FCO 500mV/DIV DCO 500mV/DIV DATA 500mV/DIV Figure 58. LVDS Output Timing Example in Reduced Range Mode Rev Page AD9257 5ns/DIV 5ns/DIV ...

  • Page 24

    ... AD9257 Figure 59 shows an example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on standard FR-4 material. 400 EYE: ALL BITS 300 200 100 0 –100 –200 –300 –400 2.5k 2.0k 1.5k 1.0k 0.5k 0 Figure 59. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less Than 24 Inches on Standard FR-4, External 100 Ω ...

  • Page 25

    ... Data Sheet Two output clocks are provided to assist in capturing data from the AD9257. The DCO is used to clock the output data and is equal to 7× the sample clock (CLK) rate for the default mode of operation. Data is clocked out of the AD9257 on the rising and falling edges of the DCO that supports double data rate (DDR) capturing ...

  • Page 26

    ... PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 12 for the initial values) and the AD9257 inverts the bit stream with relation to the ITU standard. The output is a parallel representation of the serial PN23 sequence in MSB-first format ...

  • Page 27

    ... Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the Interfacing to High Speed ADCs via SPI. Rev Page AD9257 AN-877 Application Note, ...

  • Page 28

    ... AD9257 SERIAL PORT INTERFACE (SPI) The AD9257 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

  • Page 29

    ... The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9257. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 30

    ... Table 17 (for example, Address 0x13) this address location should not be written. Default Values After the AD9257 is reset, critical registers are loaded with default values. The default values for the registers are given in Table 17, the memory map register table. ...

  • Page 31

    ... Open Open Duty cycle 0x01 stabilize 0 = off AD9257 Comments The nibbles are mirrored so that LSB or MSB first mode registers correctly. The default for the ADCs is 16-bit mode. Unique chip ID that is used to differentiate devices ...

  • Page 32

    ... AD9257 Reg. Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 0x0B Clock divide Open Open (global) 0x0C Enhancement Open Open control 0x0D Test mode (local User input test mode except for single sequence resets alternate 10 = single once 11 = alternate once (affects user input test ...

  • Page 33

    ... SDIO pull- 0x00 down Open Open Open 0x00 Open Sync Enable sync 0x00 next only AD9257 Comments User Defined Pattern 1 LSB. User Defined Pattern 1 MSB. User Defined Pattern 2 LSB. User Defined Pattern 2 MSB. Serial stream control. Default causes MSB first and the native bit stream ...

  • Page 34

    ... Bit 0. These features cannot be used with the output driver termination select. The termination selection takes precedence over the 2× driver strength on FCO and DCO when both the output driver termination and output drive are selected. AD9257 is a feature Rev Page Data Sheet ...

  • Page 35

    ... SDIO pin, which can be used to limit loading when many devices are connected to the SPI bus. User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external reference. Bits[2:0]—Open Rev Page AD9257 ...

  • Page 36

    ... POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9257 recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD) ...

  • Page 37

    ... MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9257BCPZ-40 −40°C to +85°C AD9257BCPZRL7-40 −40°C to +85°C AD9257BCPZ-65 −40°C to +85°C AD9257BCPZRL7-65 −40°C to +85°C AD9257-65EBZ RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 TOP VIEW BSC BSC SQ 0.50 0. ...

  • Page 38

    ... AD9257 NOTES Rev Page Data Sheet ...

  • Page 39

    ... Data Sheet NOTES Rev Page AD9257 ...

  • Page 40

    ... AD9257 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10206-0-10/11(0) Rev Page Data Sheet ...