AD9257 Analog Devices, AD9257 Datasheet - Page 36

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the
it is recommended that the designer become familiar with these
guidelines, which describes the special circuit connections and
layout requirements that are needed for certain pins.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9257, it is recommended that
two separate 1.8 V supplies be used. Use one supply for analog
(AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9257. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed pad on the underside of the ADC be
connected to analog ground (AGND) to achieve the best electrical
and thermal performance of the AD9257. An exposed continuous
copper plane on the PCB should mate to the
pad, Pin 0. The copper plane should have several vias to achieve
the lowest possible resistive thermal path for heat dissipation to
AD9257
AD9257
as a system,
exposed
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flow through the bottom of the PCB. These vias should be
solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a silk-
screen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
guarantees only one tie point. For detailed information on
packaging and the PCB layout of chip scale packages, see the
AN-772
the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor.
REFERENCE DECOUPLING
The VREF pin should be externally decoupled to ground with a
low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI PORT
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9257
verter inputs during critical sampling periods.
Application Note, A Design and Manufacturing Guide for
to keep these signals from transitioning at the con-
Data Sheet