AD9257 Analog Devices, AD9257 Datasheet - Page 6

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
1
2
3
4
5
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
See the
Measured on standard FR-4 material.
Can be adjusted via the SPI.
t
Wake-up time is defined as the time required to return to normal operation from power-down mode.
SAMPLE
Input Clock Rate
Conversion Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Propagation Delay (t
Rise Time (t
Fall Time (t
FCO Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Delay (t
DCO to FCO Delay (t
Data to Data Skew
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Aperture Delay (t
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
(t
/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. t
DATA-MAX
3
AN-835 Application
1
, 2
F
− t
R
) (20% to 80%)
) (20% to 80%)
DATA-MIN
A
)
PD
DATA
3
FRAME
)
)
Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
)
EL
4
EH
)
)
4
FCO
)
CPD
)
)
4
5
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
Description
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
See Figure 61
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 61)
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 61)
Min
10
10
1.5
(t
(t
Rev. 0 | Page 6 of 40
SAMPLE
SAMPLE
/28) − 300
/28) − 300
Typ
12.5/7.69
12.5/7.69
2.3
300
300
2.3
t
(t
(t
±50
35
375
1
0.1
1
16
FCO
SAMPLE
SAMPLE
+ (t
SAMPLE
/28)
/28)
SAMPLE
= 1/f
/28)
S
.
Max
520
40/65
3.1
(t
(t
±200
SAMPLE
SAMPLE
/28) + 300
/28) + 300
Limit
0.24
0.40
2
2
40
2
2
10
10
10
10
Data Sheet
Unit
MHz
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
μs
μs
Clock
cycles
ns
ps rms
Clock
cycles
Unit
ns typ
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min