AD9634

Manufacturer Part NumberAD9634
Description12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9634 datasheet
 

Specifications of AD9634

Resolution (bits)12bit# Chan1
Sample Rate250MSPSInterfaceLVDS
Analog Input TypeDiff-UniAin Range1.75 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
SNR = 69.7 dBFS at 185 MHz A
and 250 MSPS
IN
SFDR = 87 dBc at 185 MHz A
and 250 MSPS
IN
−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A
250 MSPS
Total power consumption: 360 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 350 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy-saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The
AD9634
is a 12-bit, analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The
AD9634
support communications applications where low cost, small size,
wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
The ADC output data are routed directly to the external 12-bit
LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
and
VIN+
IN
VIN–
VCM
AD9634
REFERENCE
SCLK
Programming for setup and control is accomplished using a
is designed to
3-wire, SPI-compatible serial interface.
The
AD9634
is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This product
is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
4. 3-pin, 1.8 V SPI port for register programming and readback.
5. Pin compatibility with the AD9642, allowing a simple
migration up to 14 bits, and with the AD6672.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9634
AVDD
AGND
DRVDD
PIPELINE
12
12-BIT
ADC
PARALLEL
DDR LVDS
AND
DRIVERS
1-TO-8
SERIAL PORT
CLOCK DIVIDER
SDIO
CSB
CLK+
CLK–
Figure 1.
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
D0±/D1±
.
.
.
D10±/D11±
DCO±
OR±

AD9634 Summary of contents

  • Page 1

    ... MHz. 4. 3-pin, 1.8 V SPI port for register programming and readback. 5. Pin compatibility with the AD9642, allowing a simple migration bits, and with the AD6672. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9634 AVDD AGND DRVDD PIPELINE 12 12-BIT ...

  • Page 2

    ... AD9634 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 ADC DC Specifications................................................................. 3 ADC AC Specifications ................................................................. 4 Digital Specifications ................................................................... 6 Switching Specifications ................................................................ 7 Timing Specifications .................................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 18 Theory of Operation ...

  • Page 3

    ... Rev Page AD9634 AD9634-250 Max Min Typ Max Unit 12 Bits Guaranteed ±11 ±11 mV +1/−8 +3/−7 %FSR ±0.4 ±0.4 LSB ±0.22 LSB ±0.4 ±0.6 LSB ±0.27 LSB ±7 ppm/°C ±75 ppm/° ...

  • Page 4

    ... Full 25°C −84 25°C 96 25°C 95 Full 83 25°C 97 25°C 86 Full 25°C 84 25°C −98 25°C −97 Full −87 25°C −98 25°C −95 Full 25°C −96 Rev Page AD9634-210 AD9634-250 Min Typ Max Min Typ Max 70.2 70.1 70.1 70.0 68.8 70.0 69.9 69.6 69.7 67.8 69.2 69.3 69.2 69.2 69.1 69.0 67.8 69.1 69.0 68.7 68.7 66.7 68.3 68.4 11.2 11.2 11.2 11 ...

  • Page 5

    ... Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and is not attenuated internally. AD9634-170 Temperature Min Typ Max 25°C 87 25°C 350 25°C 1000 Rev Page AD9634-210 AD9634-250 Min Typ Max Min Typ Max 89 88 350 350 1000 1000 AD9634 Unit dBc MHz MHz ...

  • Page 6

    ... AD9634 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range ...

  • Page 7

    ... – – – – – 6 D10 D11 D10 D11 D10 N – – – – – 6 AD9634 Unit MHz MSPS MSPS rms Cycles μs μs Cycles ...

  • Page 8

    ... AD9634 TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments SPI TIMING REQUIREMENTS See Figure 58 for the SPI timing diagram t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK DH t Period of the SCLK ...

  • Page 9

    ... ESD CAUTION Rev Page Airflow Velocity (m/sec) θ θ 37.1 3.1 1.0 32.4 2.0 29.1 is specified for a 4-layer PCB with solid ground plane addition, metal in direct contact with the package AD9634 1, 4 θ Unit JB 20.7 °C/W °C/W °C/W ...

  • Page 10

    ... D10−/ D11− (MSB) 21 DCO+ 20 DCO− CLK CSB 2 23 SCLK CLK– AVDD 3 22 SDIO AD9634 OR– DCO+ TOP VIEW 5 20 DCO– OR+ (Not to Scale D10+/D11+ (MSB) D0–/D1– (LSB D10–/D11– (MSB) ...

  • Page 11

    ... Pin No. Mnemonic SPI Control 23 SCLK 22 SDIO 24 CSB Type Description Input SPI Serial Clock. Input/Output SPI Serial Data I/O. Input SPI Chip Select (Active Low). Rev Page AD9634 ...

  • Page 12

    ... MHz IN 100 SECOND 80 HARMONIC Figure 9. AD9634-170 Single-Tone SNR/SFDR vs. Input Frequency (f = 220.1 MHz IN Rev Page 170MSPS 305.1MHz @ –1.0dBFS SNR = 67.2dB (68.2dBFS) SFDR = 86dBc THIRD HARMONIC FREQUENCY (MHz) = 305.1 MHz ...

  • Page 13

    ... FREQUENCY (MHz) Figure 12. AD9634-170 Two-Tone FFT with f = 89.12 MHz, f IN1 –100 –120 –140 ) with Figure 13. AD9634-170 Two Tone FFT with 170 MSPS S 100 ) Figure 14. AD9634-170 Single-Tone SNR/SFDR vs. Sample Rate ( 170 MSPS S 14000 12000 10000 8000 6000 4000 2000 92.12 MHz Figure 15 ...

  • Page 14

    ... MHz Figure 19. AD9634-210 Single-Tone FFT with f IN 120 100 80 THIRD 60 HARMONIC 105 Figure 20. AD9634-210 Single-Tone SNR/SFDR vs. Input Amplitude (A = 185.1 MHz IN 100 105 Figure 21. AD9634-210 Single-Tone SNR/SFDR vs. Input Frequency (f = 220.1 MHz IN Rev Page 210MSPS 305.1MHz @ – ...

  • Page 15

    ... FREQUENCY (MHz) Figure 24. AD9634-210 Two-Tone FFT with f = 89.12 MHz, f IN1 –100 –120 –140 ) with Figure 25. AD9634-210 Two Tone FFT with 210 MSPS S 100 ) with Figure 26. AD9634-210 Single-Tone SNR/SFDR vs. Sample Rate ( 210 MSPS S 16000 14000 12000 10000 8000 6000 4000 2000 75 90 105 = 92 ...

  • Page 16

    ... MHz IN 120 100 SECOND HARMONIC 100 125 Figure 32. AD9634-250 Single-Tone SNR/SFDR vs. Input Amplitude (A = 185.1 MHz IN 100 THIRD HARMONIC 100 125 Figure 33. AD9634-250 Single-Tone SNR/SFDR vs. Input Frequency (f = 220.1 MHz IN Rev Page 250MSPS 305.1MHz @ –1.0dBFS SNR = 67 ...

  • Page 17

    ... FREQUENCY (MHz) Figure 36. AD9634-250 Two-Tone FFT with f = 89.12 MHz, f IN1 –100 –120 –140 ) with Figure 37. AD9634-250 Two Tone FFT with 250 MSPS S 100 ) Figure 38. AD9634-250 Single-Tone SNR/SFDR vs. Sample Rate ( 250 MSPS S 16000 14000 12000 10000 8000 6000 4000 2000 100 125 = 92 ...

  • Page 18

    ... AD9634 EQUIVALENT CIRCUITS AVDD VIN Figure 40. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 41. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 42. Equivalent LVDS Output Circuit AVDD CLK– Rev Page DRVDD 350Ω ...

  • Page 19

    ... Rev Page AN-742 Application Note, Frequency Domain AN-827 Application “Transformer- Converters” for more BIAS PAR2 PAR2 S BIAS Figure 46. Switched-Capacitor Input AD9634 are not internally dc biased 0.5 × AVDD (or 0 AD9634 S ...

  • Page 20

    ... VCM VIN+ the true SNR performance of the AD9634. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49). In this 0.1µF configuration, the input is ac-coupled and the VCM voltage is ADA4930-1 provided to each input through a 33 Ω ...

  • Page 21

    ... V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9634, while preserving the fast rise and fall times of the signal, which are critical for low jitter performance. CLOCK ...

  • Page 22

    ... Figure 56. AD9634-250 SNR vs. Input Frequency and Jitter In cases where aperture jitter may affect the dynamic range of the AD9634, treat the clock input as an analog signal. In addition, use separate power supplies for the clock drivers and the ADC output driver to avoid modulating the clock signal with digital noise ...

  • Page 23

    ... PD Minimize the length of the output data lines as well as the loads placed on these lines to reduce transients within the AD9634. These transients may degrade converter dynamic performance. The lowest typical conversion rate of the clock rates below 40 MSPS, dynamic performance can degrade. ...

  • Page 24

    ... The pins described in Table 11 comprise the physical interface between the user programming device and the serial port of the AD9634. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. ...

  • Page 25

    ... Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage Allows the user to enable the synchronization features DON’T CARE AD9634 DON’T CARE ...

  • Page 26

    ... Address 0x18). If the entire address location is open (for example, Address 0x13), do not write to this address location. Default Values After the AD9634 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 13). ...

  • Page 27

    ... Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0], AD9634 = 0x87 (default) Speed grade ID; Open Open 00 = 250 MSPS 01 = 210 MSPS 11 = 170 MSPS Open Open Open Open Open Open Open Open Open ...

  • Page 28

    ... AD9634 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST enable Open Open 0x10 Offset adjust Open Open 0x14 Output mode Open Open 0x15 Output adjust Open Open 0x16 Clock phase Invert Open control DCO clock 0x17 Open DCO output Enable ...

  • Page 29

    ... Power and Ground Recommendations When connecting power to the AD9634 recommended that two separate 1.8 V supplies be used: use one supply for analog (AVDD) and a separate supply for digital outputs (DRVDD). ...

  • Page 30

    ... Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board with AD9634 and Software Evaluation Board with AD9634 and Software Evaluation Board with AD9634 and Software Rev Page ...

  • Page 31

    ... NOTES Rev Page AD9634 ...

  • Page 32

    ... AD9634 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09996-0-7/11(0) Rev Page ...