AD9634 Analog Devices, AD9634 Datasheet - Page 19

• Manufacturer Part Number: AD9634
• Description: 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9634

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

THEORY OF OPERATION
The
250 MHz using appropriate low-pass or band-pass filtering at
the ADC inputs with little loss in ADC performance.
Programming and control of the
using a 3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The
hold circuit, followed by a pipelined, switched-capacitor ADC.
The quantized outputs from each stage are combined into a
final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage contains a differential sampling circuit that can
be ac- or dc-coupled in differential or single-ended modes. The
output staging block aligns the data, corrects errors, and passes the
data to the output buffers. The output buffers are powered from a
separate supply, allowing digital output noise to be separated from
the analog core. During power-down, the output buffers go into
a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the
circuit that has been designed to attain optimum performance
when processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 46).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within ½ clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
AD9634
AD9634
can sample any f
architecture consists of a front-end sample-and-
AD9634
S
/2 frequency segment from dc to
is a differential switched-capacitor
AD9634
are accomplished
Rev. 0 | Page 19 of 32
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the
Response of Switched-Capacitor ADCs; the
Note, A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article,
Coupled Front-End for Wideband A/D
information on this subject.
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the
ac-coupled applications, the user must provide this bias externally.
Setting the device so that V
recommended for optimum performance. An on-board common-
mode voltage reference is included in the design and is available
from the VCM pin. Using the VCM output to set the input
common mode is recommended. Optimum performance is
achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). The
VCM pin must be decoupled to ground by a 0.1 μF capacitor,
as described in the Applications Information section. Place this
decoupling capacitor close to the pin to minimize the series
resistance and inductance between the part and this capacitor.
VIN+
VIN–
C
C
PAR1
PAR1
AN-742 Application
S
S
Figure 46. Switched-Capacitor Input
C
C
PAR2
PAR2
AD9634
H
CM
C
C
= 0.5 × AVDD (or 0.9 V) is
S
S
BIAS
BIAS
Note, Frequency Domain
are not internally dc biased. In
Converters” for more
S
S
S
AN-827 Application
C
C
“Transformer-
FB
FB
AD9634
S