AD9642

Manufacturer Part NumberAD9642
Description14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
ManufacturerAnalog Devices
AD9642 datasheet
 

Specifications of AD9642

Resolution (bits)14bit# Chan1
Sample Rate250MSPSInterfaceLVDS
Analog Input TypeDiff-Bip,Diff-UniAin Range1.75 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
SNR = 71.0 dBFS at 185 MHz A
and 250 MSPS
IN
SFDR = 83 dBc at 185 MHz A
and 250 MSPS
IN
−152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS A
Total power consumption: 390 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 350 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The
AD9642
is a 14-bit analog-to-digital converter (ADC) with
sampling speeds of up to 250 MSPS. The
support communications applications, where low cost, small
size, wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs that can support a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer (DCS) is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converter to maintain excellent performance.
The ADC output data is routed directly to the external
14-bit LVDS output port.
Flexible power-down options allow significant power savings,
when desired.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
14-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter (ADC)
VIN+
, 250 MSPS
IN
VIN–
VCM
Programming for setup and control is accomplished using a
AD9642
is designed to
3-wire SPI-compatible serial interface.
The
AD9642
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
2.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
3.
Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 350 MHz.
4.
3-pin, 1.8 V SPI port for register programming and readback.
5.
Pin compatibility with the AD9634, allowing a simple migra-
tion from 14 bits to 12 bits, and with the AD6672.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9642
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
PIPELINE
14
14-BIT
ADC
AD9642
PARALLEL
DDR LVDS
AND
DRIVERS
REFERENCE
1-TO-8
SERIAL PORT
CLOCK
DIVIDER
SCLK
SDIO
CSB
CLK+
CLK–
Figure 1.
is available in a 32-lead LFCSP and is specified
©2011 Analog Devices, Inc. All rights reserved.
D0±/D1±
D12±/D13±
DCO±
www.analog.com

AD9642 Summary of contents

  • Page 1

    ... AD6672. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9642 FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD PIPELINE 14 14-BIT ADC AD9642 PARALLEL DDR LVDS AND DRIVERS REFERENCE 1-TO-8 SERIAL PORT CLOCK DIVIDER SCLK SDIO CSB CLK+ CLK– ...

  • Page 2

    ... AD9642 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 ADC DC Specifications ............................................................... 3 ADC AC Specifications ............................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Specifications .................................................................. 7 Absolute Maximum Ratings............................................................ 8 Thermal Characteristics .............................................................. 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 10 Equivalent Circuits ......................................................................... 16 REVISION HISTORY 7/11— ...

  • Page 3

    ... Rev Page AD9642 AD9642-250 Max Min Typ Max Unit 14 Bits Guaranteed ±11 ±10 mV +3.5/−8 +3/−7 %FSR ±0.55 ±0.6 LSB ±0.32 LSB ±2.0 ±2.5 LSB ±1.0 LSB ±7 ppm/°C ±75 ppm/°C ...

  • Page 4

    ... Full 25°C −84 25°C 96 25°C 95 Full 82 25°C 97 25°C 86 Full 25°C 84 25°C −99 25°C −95 Full −87 25°C −98 25°C −96 Full 25°C −97 25°C 87 Rev Page AD9642-210 AD9642-250 Min Typ Max Min Typ 72.4 72.2 72.2 72.0 70.0 71.6 71.8 71.5 71.4 68.6 71.0 70.9 71.5 71.2 71.3 71.0 68.7 70.6 70.9 70.5 70.4 67.5 70.1 70.0 11.6 11.5 11.6 11.5 11.4 11.5 11 ...

  • Page 5

    ... AD9642 Max Unit MHz MHz Unit μA μA pF kΩ μA μA kΩ μA μA kΩ μA μA kΩ ...

  • Page 6

    ... CLK t DCO t SKEW – – – – 9 D12 D13 D12 N – – – – 9 Figure 2. LVDS Data Output Timing Rev Page AD9642-210 AD9642-250 Typ Max Min Typ 625 210 40 4 2.4 2.64 1.8 2.0 2.4 2.52 1.9 2.0 0.8 1.0 1.0 0.1 0.1 4.7 5.2 4.1 4.7 5.3 5 ...

  • Page 7

    ... Time required for the SDIO pin to switch from an input to an output EN_SDIO relative to the SCLK falling edge (not shown in Figure 58) t Time required for the SDIO pin to switch from an output to an input DIS_SDIO relative to the SCLK rising edge (not shown in Figure 58) Rev Page AD9642 Min Typ Max Unit ...

  • Page 8

    ... AD9642 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND D0−/D1−, D0+/D1+ Through D12−/D13−, D12+/D13+ to AGND DCO+, DCO− to AGND ...

  • Page 9

    ... DDR LVDS Output Data 12/13—True. Output DDR LVDS Output Data 12/13—Complement. Output LVDS Data Clock Output—True. Output LVDS Data Clock Output—Complement. Input SPI Serial Clock. Input/output SPI Serial Data I/O. Input SPI Chip Select (Active Low). Rev Page AD9642 This pin should be decoupled ...

  • Page 10

    ... MHz IN THIRD HARMONIC 185.1 MHz IN SECOND HARMONIC 220.1 MHz Figure 9. AD9642-170 Single-Tone SNR/SFDR vs. Input Frequency (f IN Rev Page 170MSPS 305.1MHz @ –1dBFS –20 SNR = 68.0dB (69.0dBFS) SFDR = 86dBc –40 –60 SECOND HARMONIC THIRD HARMONIC –80 –100 –120 – ...

  • Page 11

    ... FREQUENCY (MHz) Figure 12. AD9642-170 Two-Tone FFT with f = 89.12 MHz, f IN1 –100 –120 –140 ) with Figure 13. AD9642-170 Two Tone FFT with 170 MSPS S 100 Figure 14. AD9642-170 Single-Tone SNR/SFDR vs. Sample Rate ( 170 MSPS S 6000 5000 4000 3000 2000 1000 92.12 MHz Figure 15 ...

  • Page 12

    ... Figure 19. AD9642-210 Single-Tone FFT with f = 90.1 MHz IN 120 100 80 60 THIRD HARMONIC 105 –100 = 185.1 MHz Figure 20. AD9642-210 Single-Tone SNR/SFDR vs. Input Amplitude (A IN 100 105 Figure 21. AD9642-210 Single-Tone SNR/SFDR vs. Input Frequency (f = 220.1 MHz IN Rev Page ...

  • Page 13

    ... IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS) Figure 22. AD9642-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 89.12 MHz 92.12 MHz, f IN1 IN2 0 –20 SFDR (dBc) –40 IMD3 (dBc) – ...

  • Page 14

    ... FREQUENCY (MHz) Figure 30. AD9642-250 Single-Tone FFT with f 100 125 = 90.1 MHz IN SECOND HARMONIC 100 125 Figure 32. AD9642-250 Single-Tone SNR/SFDR vs. Input Amplitude (A = 185.1 MHz IN 100 125 = 220.1 MHz Figure 33. AD9642-250 Single-Tone SNR/SFDR vs. Input Frequency (f IN Rev Page 250MSPS 305.1MHz @ –1dBFS – ...

  • Page 15

    ... Figure 37. AD9642-250 Two Tone FFT with 250 MSPS S 100 –7.0 ) Figure 38. AD9642-250 Single-Tone SNR/SFDR vs. Sample Rate ( 250 MSPS S 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 100 125 = 92.12 MHz Figure 39. AD9642-250 Grounded Input Histogram, f IN2 Rev ...

  • Page 16

    ... AD9642 EQUIVALENT CIRCUITS AVDD VIN Figure 40. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 41. Equivalent Clock Input Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 42. Equivalent LVDS Output Circuit AVDD CLK– Rev Page DRVDD 350Ω ...

  • Page 17

    ... S C PAR1 S PAR2 S BIAS Figure 46. Switched-Capacitor Input AD9642 are not internally dc biased. = 0.5 × AVDD (or CM ADA4930-1 differential drivers ADA4930-1 AD9642 (see Figure 47), and the 15pF 200Ω 33Ω 15Ω 90Ω 76.8Ω 5pF ADA4930-1 33Ω 15Ω 120Ω 15pF 200Ω AD9642 Converters, ” ...

  • Page 18

    ... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9642. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 50). In this configuration, the input is ac-coupled and the VCM voltage is provided to each input through a 33 Ω ...

  • Page 19

    ... VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9642. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly. CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9642 CLK+ and CLK− ...

  • Page 20

    ... Figure 56. AD9642-250 SNR vs. Input Frequency and Jitter In cases where aperture jitter may affect the dynamic range of the AD9642, treat the clock input as an analog signal. In addition, use separate power supplies for the clock drivers and the ADC output driver to avoid modulating the clock signal with digital noise ...

  • Page 21

    ... PD Minimize the length of the output data lines as well as the loads placed on these lines to reduce transients within the AD9642. These transients may degrade converter dynamic performance. Table 10. Output Data Format VIN+ − VIN−, Input (V) Input Span = 1 ...

  • Page 22

    ... The pins described in Table 11 comprise the physical interface between the user programming device and the serial port of the AD9642. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 23

    ... Allows the user to enable the synchronization features CSB DON’T SCLK CARE DON’T R A12 SDIO CARE t HIGH t CLK t LOW A11 A10 Figure 58. Serial Port Interface Timing Diagram Rev Page AD9642 DON’T CARE DON’T CARE ...

  • Page 24

    ... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9642 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (Table 13). ...

  • Page 25

    ... FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output Rev Page AD9642 Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments LSB first ...

  • Page 26

    ... AD9642 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x0E BIST enable Open Open 0x10 Offset adjust Open Open 0x14 Output mode Open Open 0x15 Output adjust Open Open 0x16 Clock phase Invert Open control DCO clock 0x17 DCO output Enable Open ...

  • Page 27

    ... Power and Ground Recommendations When connecting power to the AD9642 recommended that two separate 1.8 V supplies be used: use one supply for analog (AVDD) and a separate supply for the digital outputs (DRVDD). ...

  • Page 28

    ... Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board with AD9642 and Software Evaluation Board with AD9642 and Software Evaluation Board with AD9642 and Software D09995-0-7/11(0) Rev ...