AD9642 Analog Devices, AD9642 Datasheet - Page 19

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AD9642

Manufacturer Part Number
AD9642
Description
14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
Manufacturer
Analog Devices
Datasheet

Specifications of AD9642

Resolution (bits)
14bit
# Chan
1
Sample Rate
250MSPS
Interface
LVDS
Analog Input Type
Diff-Bip,Diff-Uni
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

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VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9642.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference voltage
changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 51) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
Clock Input Options
The
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 52 and Figure 53 show two preferable methods for
clocking the
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from
10 MHz to 200 MHz. The back-to-back Schottky diodes across
the secondary winding of the transformer limit clock excursions
into the
limit helps prevent the large voltage swings of the clock from
feeding through to other portions of the
preserving the fast rise and fall times of the signal, which are
critical for low jitter performance.
CLOCK
INPUT
AD9642
Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLK+
AD9642
Figure 51. Simplified Equivalent Clock Input Circuit
50Ω
390pF
AD9642
has a very flexible clock input structure. Clock input
100Ω
4pF
to approximately 0.8 V p-p differential. This
ADT1-1WT, 1:1Z
Mini-Circuits
(at clock rates of up to 625 MHz). A low
XFMR
AVDD
0.9V
390pF
®
390pF
AD9642
SCHOTTKY
HSMS2822
DIODES:
AD9642
sample clock inputs,
4pF
while
CLK+
CLK–
CLK–
ADC
Rev. 0 | Page 19 of 28
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 54. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,
AD9522, AD9523, AD9524, and
ADCLK925
CLOCK
CLOCK
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,
AD9518, AD9520, AD9522, AD9523, and
offer excellent jitter performance.
CLOCK
CLOCK
Input Clock Divider
The
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The
edge, providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock input
duty cycles without affecting the performance of the AD9642.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
INPUT
INPUT
INPUT
INPUT
CLOCK
AD9642
AD9642
INPUT
50kΩ
50kΩ
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
390pF
clock drivers offer excellent jitter performance.
contains a DCS that retimes the nonsampling (falling)
contains an input clock divider with the ability to
1nF
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ
50kΩ
AD95xx,
ADCLK9xx
PECL DRIVER
AD95xx
LVDS DRIVER
25Ω
25Ω
240Ω
390pF
390pF
ADCLK905/ADCLK907/
SCHOTTKY
HSMS2822
DIODES:
240Ω
0.1µF
0.1µF
AD9524
100Ω
0.1µF
0.1µF
100Ω
CLK+
CLK–
ADC
clock drivers
CLK+
CLK–
CLK+
CLK–
AD9642
AD9642
AD9642
ADC
ADC

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