AD9648

Manufacturer Part NumberAD9648
Description14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9648 datasheet
 


Specifications of AD9648

Resolution (bits)14bit# Chan2
Sample Rate125MSPSInterfacePar
Analog Input TypeDiff-UniAin Range(2Vref) p-p,2 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS outputs
SNR = 74.5 dBFS @ 70 MHz
SFDR = 91 dBc @ 70 MHz
Low power: 78 mW/channel ADC core @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.35 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
1
This product is protected by a U.S patent.
Rev.
0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
VIN+A
ADC
VIN–A
VREF
SENSE
AD9648
REF
VCM
SELECT
RBIAS
VIN–B
ADC
VIN+B
DIVIDE
1 TO 8
CLK+ CLK–
SYNC
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1.
The
AD9648
1
operates from a single 1.8 V analog
power supply and features a separate digital output
driver supply to accommodate 1.8 V CMOS or LVDS
logic families.
2.
The patented sample-and-hold circuit maintains
excellent performance for input frequencies up to
200 MHz and is designed for low cost, low power, and
ease of use.
3.
A standard serial port interface supports various
product features and functions, such as data output
formatting, internal clock divider, power-down,
DCO/data timing and offset adjustments.
4.
The
AD9648
is packaged in a 64-lead RoHS compliant
LFCSP that is pin compatible with the AD9650/
AD9269/AD9268
16-bit ADC, the
ADC, the
AD9628/AD9231
AD9608/AD9204
10-bit ADCs, enabling a simple
migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©
2011
AD9648
SDIO
SCLK
CSB
SPI
ORA
PROGRAMMING DATA
D13A
D0A
DCOA
DRVDD
ORB
D13B
D0B
DCOB
DUTY CYCLE
MODE
STABILIZER
CONTROLS
DCS
PDWN DFS
OEB
AD9258
14-bit
12-bit ADCs, and the
www.analog.com
Analog Devices, Inc. All rights reserved.

AD9648 Summary of contents

  • Page 1

    ... AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 © 2011 AD9648 SDIO SCLK CSB SPI ORA PROGRAMMING DATA D13A D0A DCOA ...

  • Page 2

    ... Digital Specifications ................................................................... 6 Switching Specifications ................................................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 12 Thermal Characteristics ............................................................ 12 ESD Caution ................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Typical Performance Characteristics ........................................... 19 AD9648-125 ................................................................................ 20 AD9648-105 ................................................................................ 22 Equivalent Circuits ......................................................................... 24 Theory of Operation ...................................................................... 25 ADC Architecture ...................................................................... 25 Analog Input Considerations .................................................... 25 REVISION HISTORY 7/11—Revision 0: Initial Version   Voltage Reference ....................................................................... 27   ...

  • Page 3

    ... Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus. The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent. Rev Page AD9648 ...

  • Page 4

    ... Full 2 Full 5 Full 7.5 Full 0.9 Full 0.5 1.3 Full 1.7 1.8 1.9 Full 1.7 1.8 1.9 Full 81 86 Full 19.2 Full 63.5 Rev Page AD9648-125 Min Typ Max Unit 14 Bits Guaranteed −0.8 −0.3 +0.2 % FSR −5.1 ±1.3 +5.1 % FSR −0.5 +1.2 LSB ±0.5 LSB −2.3 +2.3 LSB ±1.0 LSB ±0.01 ±0.58 % FSR ±0.5 ± ...

  • Page 5

    ... Full −86 25°C −92 25°C −81 Rev Page AD9648 AD9648-125 Min Typ Max Unit 155.5 mW 202.5 211.5 mW 211.5 220.5 mW 120 mW 2.0 mW AD9648-125 Min Typ Max Unit 75.0 dBFS 74.7 dBFS 74.5 dBFS 73.0 dBFS 73.9 dBFS 71.5 dBFS 73.9 dBFS 73.4 dBFS 73.3 dBFS 72.8 dBFS 72.8 dBFS 70.3 dBFS 11 ...

  • Page 6

    ... Full Full 0.3 Full AGND - 0.3 Full 0.9 Full −10 Full −10 Full Full 8 Full 1.22 Full 0 Full −10 Full 40 Full Full Rev Page AD9648-125 Min Typ Max Unit dBc 96 dBc 90 dBc 91 dBc 82 dBc 90 dBc 84 dBc −97 dBc −97 dBc −97 dBc −90 dBc − ...

  • Page 7

    ... Full 0 Full −90 Full −10 Full 26 Full 5 Full 1.79 Full 1.75 Full Full Full 290 345 Full 1.15 1.25 Full 160 200 Full 1.15 1.25 Rev Page AD9648 Max Unit DRVDD + 0.2 V 0.6 V −135 μA +10 μA kΩ pF DRVDD + 0.2 V 0.6 V +10 μA 128 μA kΩ pF DRVDD + 0.2 V 0.6 V −134 μA +10 μ ...

  • Page 8

    ... Full 4.76 Full 1.0 Full 0.07 Full 1.8 2.9 4.4 Full 2.0 3.1 4.4 Full −1.2 −0.1 +1.0 Full 2.4 Full 2.4 Full −0.20 +0.03 +0.25 Full 16 Full 16/16.5 Full 350 Full 250 Full 2 Rev Page AD9648-125 Min Typ Max Unit 1000 MHz 20 125 MSPS 10 125 MSPS 1.0 ns 0.07 ps rms 1.8 2.9 4.4 ns 2.0 3.1 4.4 ns −1.2 −0.1 +1.0 ns 2.4 ns 2.4 ns − ...

  • Page 9

    ... N – – Figure 2. CMOS Default Output Mode Data Output Timing Rev Page Limit 0.24 0. – – – 12 AD9648 Unit ns typ ns typ ns min ns min ns min ns min ns min ns min ns min ns min ns min ...

  • Page 10

    ... AD9648 N – 1 VIN t CH CLK+ CLK– DCOA/DCOB CH A DATA CH B DATA VIN CLK+ CLK– DCO+ DCO– D0+ (LSB) D0– (LSB) PARALLEL INTERLEAVED MODE D13+ (MSB) D13– (MSB) D1+/0+ (LSB) CHANNEL D1–/D0– (LSB) MULTIPLEXED MODE D13+/D12+ (MSB) CHANNEL A D13– ...

  • Page 11

    ... CLK SSYNC HSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev Page AD9648 ...

  • Page 12

    ... AD9648 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical 1 AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B through D13A/D13B to AGND DCOA/DCOB to AGND ...

  • Page 13

    ... Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Digital Synchronization Pin. Slave mode only. Rev Page AD9648 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS ...

  • Page 14

    ... AD9648 Pin No. Mnemonic Type Digital Outputs 27 D0A (LSB) Output 29 D1A Output 30 D2A Output 31 D3A Output 32 D4A Output 33 D5A Output 34 D6A Output 35 D7A Output 36 D8A Output 38 D9A Output 39 D10A Output 40 D11A Output 41 D12A Output 42 D13A (MSB) Output 43 ORA Output 6 D0B (LSB) Output ...

  • Page 15

    ... ADC Clock Input—Complement. Digital Synchronization Pin. Slave mode only. Channel A/Channel B LVDS Output Data 0—True. Channel A/Channel B LVDS Output Data 0—Complement. Channel A/Channel B LVDS Output Data 1—True. Channel A/Channel B LVDS Output Data 1—Complement. Rev Page AD9648 48 PDWN 47 OEB 46 CSB ...

  • Page 16

    ... AD9648 Pin No. Mnemonic Type 14 D2+ Output 13 D2− Output 16 D3+ Output 15 D3− Output 18 D4+ Output 17 D4− Output 21 D5+ Output 20 D5− Output 23 D6+ Output 22 D6− Output 27 D7+ Output 26 D7− Output 30 D8+ Output 29 D8− Output 32 D9+ Output 31 D9− ...

  • Page 17

    ... Reference Mode Selection. Input/Output External Reference Bias Resistor. Output Common-Mode Level Bias Output for Analog Inputs. Input ADC Clock Input—True. Input ADC Clock Input—Complement. Input Digital Synchronization Pin. Slave mode only. Rev Page AD9648 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS 44 SDIO/DCS 43 ...

  • Page 18

    ... AD9648 Pin No. Mnemonic Digital Outputs 8 B D1−/D0− (LSB D1+/D0+ (LSB D3−/D2− D3+/D2 D5−/D4− D5+/D4 D7−/D6− D7+/D6 D9−/D8− D9+/D8 D11−/D10− D11+/D10 D13−/D12− (MSB) ...

  • Page 19

    ... FREQUENCY (MHz) Figure 12. Single-Tone FFT with f = 100.5 MHz IN 0 125MSPS 200.5MHz AT –1dBFS SNR = 70.9dB (71.9dBFS) –20 SFDR = 83.6dBc –40 –60 – FREQUENCY (MHz) Figure 13. Single-Tone FFT with f = 200.5 MHz IN AD9648 ...

  • Page 20

    ... AD9648 AD9648-125 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted –15 –15 –30 –30 –45 –45 –60 –60 –75 –75 2F1 – F2 –90 –90 –105 –105 –120 –120 –135 –135 ...

  • Page 21

    ... Figure 20. DNL Error with f = 9.7 MHz IN 450,000 400,000 350,000 300,000 250,000 200,000 150,000 100,000 50,000 0 OUTPUT CODE Figure 21. Shorted Input Histogram 2.0 1.5 1.0 0.5 0 -0.5 –1.0 –1.5 –2.0 0 2000 4000 6000 Figure 22. INL Error with f Rev Page AD9648 8000 10000 12000 14000 16000 OUTPUT CODE = 9.7 MHz IN ...

  • Page 22

    ... AD9648 AD9648-105 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 105MSPS 9.7MHz AT –1dBFS SNR = 74.7dB (75.7dBFS) SFDR = 98.7dBc –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 23. Single-Tone FFT with f ...

  • Page 23

    ... INPUT AMPLITUDE (dBFS) SFDR (dBc) SNR (dBFS SAMPLE RATE (MSPS) Figure 32. SNR/SFDR vs. Sample Rate with AIN = 70.1 MHz 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE Figure 33. INL Error with f = 9.7 MHz IN AD9648 0 –10 = 9.7 MHz 105 ...

  • Page 24

    ... AD9648 EQUIVALENT CIRCUITS AVDD VIN±x Figure 34. Equivalent Analog Input Circuit 5Ω CLK+ 15kΩ 15kΩ 5Ω CLK– Figure 35. Equivalent Clock Input Circuit DRVDD PAD Figure 36. Equivalent Digital Output Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ ...

  • Page 25

    ... See the AN-742 Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Rev Page AD9648 is a differential switched PAR H C ...

  • Page 26

    ... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9648. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 46). ...

  • Page 27

    ... Figure 48. Single-Ended Input Configuration VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9648. The VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference ...

  • Page 28

    ... Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz) sample clock CLOCK INPUT CLK– 2pF Rev Page has a very flexible clock input structure. The clock AD9648 (at clock rates GHz prior to internal CLK AD9648 AD9648 ® Mini-Circuits ADT1-1WT, 1:1 Z 0.1µF 0.1µF XFMR 100Ω 50Ω ...

  • Page 29

    ... This allows the user to CLK+ provide a wide range of clock input duty cycles without affecting 100Ω ADC the performance of the AD9648. Noise and distortion perform- 0.1µF CLK– ance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 58. ...

  • Page 30

    ... Figure 60. AD9648-125 Power and Current vs. Clock Rate (1.8 V CMOS 90 AN-756 Application Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOS Rev Page × C × f × N DRVDD ...

  • Page 31

    ... Data outputs are available one propagation delay (t Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9648. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the At clock rates below 10 MSPS, dynamic performance can degrade. ...

  • Page 32

    ... A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the is included. Various output test options are also provided to place predictable values on the outputs of the AD9648. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9648 signal path ...

  • Page 33

    ... For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t CLK t LOW A11 A10 Figure 62. Serial Port Interface Timing Diagram Rev Page DON’T CARE AD9648 DON’T CARE ...

  • Page 34

    ... The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9648. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 35

    ... If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 18 affect the entire part or the channel features for which independent settings are not allowed between channels. Rev Page AD9648 ...

  • Page 36

    ... Power Open Open modes (local) 0x09 Global Open Open clock (global) Bit 5 Bit 4 Bit 3 Soft reset 1 1 8-bit chip ID[7:0] AD9648 = 0x88 Open Open Open Open Open Open External Open Open power- down pin function 0 = PDWN 1 = standby Open Open Open Rev Page ...

  • Page 37

    ... Delay selection 0x00 000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns AD9648 Comments The divide ratio is value plus 1 Chop mode enabled if Bit 2 is enabled When this register is set, the test data is ...

  • Page 38

    ... AD9648 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x18 VREF Open Open select (global) 0x19 User B7 B6 Pattern 1 LSB (global) 0x1A User B15 B14 Pattern 1 MSB (global) 0x1B User B7 B6 Pattern 2 LSB (global) 0x1C User B15 B14 Pattern 2 MSB 0x24 MISR LSB ...

  • Page 39

    ... Sample Rate Override (Register 0x100) This register is designed to allow the user to downgrade the device. Any attempt to upgrade the default speed grade results in a chip power-down. Settings in this register are not initialized until Bit 0 of the transfer register (Register 0xFF) is written high. Rev Page AD9648 ...

  • Page 40

    ... AD9648 User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled. If Bit 7 is clear, the OEB pin is disabled (default). Bits[6:1]—Open Bit 0—SDIO Pull-Down Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus ...

  • Page 41

    ... LVDS mode. This additional DRVDD current does not cause damage to the AD9648, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the can be disabled at power-up by taking the PDWN pin high ...

  • Page 42

    ... TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9648BCPZ-105 −40°C to +85°C AD9648BCPZ-125 −40°C to +85°C AD9648BCPZRL7-105 −40°C to +85°C AD9648BCPZRL7-125 −40°C to +85°C AD9648-125EBZ RoHS Compliant Part. 0.60 MAX 48 0.50 8.75 BSC BSC SQ 0.50 33 0.40 0.30 0.80 MAX ...

  • Page 43

    ... NOTES Rev Page AD9648 ...

  • Page 44

    ... AD9648 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09975-0-7/11(0) Rev Page ...