AD9648 Analog Devices, AD9648 Datasheet - Page 14

• Manufacturer Part Number: AD9648
• Description: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9648

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9648
Pin No.
Digital Outputs
27
29
30
31
32
33
34
35
36
38
39
40
41
42
43
6
7
8
9
11
12
13
14
15
16
17
18
20
21
22
24
23
SPI Control
45
44
46
ADC Configuration
47
48
Mnemonic
D0A (LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
D11A
D12A
D13A (MSB)
ORA
D0B (LSB)
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
D12B
D13B (MSB)
ORB
DCOA
DCOB
SCLK/DFS
SDIO/DCS
CSB
OEB
PDWN
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input/Output
Input
Input
Input
Description
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A Overrange Output.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B Overrange Output
Channel A Data Clock Output.
Channel B Data Clock Output.
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Output Enable Input (Active Low). Pin must be enabled via SPI.
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured
as power-down or standby.
Rev. 0 | Page 14 of 44