AD9648 Analog Devices, AD9648 Datasheet - Page 28

• Manufacturer Part Number: AD9648
• Description: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9648

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9648
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 51 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 41). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 52) and require no external bias.
CLK+
–1
–2
–3
–4
–5
–6
4
3
2
1
0
–40
–20
2pF
Figure 52. Equivalent Clock Input Circuit
Figure 51. Typical V
0
V
REF
TEMPERATURE (°C)
AVDD
ERROR (mV)
0.9V
20
REF
AD9648
Drift
40
sample clock
60
2pF
CLK–
80
Rev. 0 | Page 28 of 44
CLOCK
Clock Input Options
The
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
Figure 53 and Figure 54 show two preferred methods for clock-
ing the
divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF
transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1 GHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
CLOCK
INPUT
INPUT
AD9648
Figure 53. Transformer-Coupled Differential Clock (Up to 200 MHz)
AD9648
Figure 54. Balun-Coupled Differential Clock (Up to 1 GHz)
50Ω
50Ω
0.1µF
has a very flexible clock input structure. The clock
1nF
1nF
(at clock rates up to 1 GHz prior to internal CLK
100Ω
ADT1-1WT, 1:1 Z
Mini-Circuits
XFMR
0.1µF
®
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
AD9648
AD9648
CLK+
CLK–
CLK+
CLK–
to
ADC
while
ADC