AD6643

Manufacturer Part NumberAD6643
DescriptionDual IF Receiver
ManufacturerAnalog Devices
AD6643 datasheet
 


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Data Sheet
FEATURES
Performance with NSR enabled
SNR: 76.1 dBFS in a 40 MHz band to 90 MHz at 185 MSPS
SNR: 73.6 dBFS in a 60 MHz band to 90 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS up to 90 MHz at 185 MSPS
SFDR: 88 dBc up to 185 MHz at 185 MSPS
Total power consumption: 706 mW at 200 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
Differential analog inputs with 400 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel
intermediate frequency (IF) receiver specifically designed to
support multi-antenna systems in telecommunication
applications where high dynamic range performance, low power,
and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic, and
each ADC features a wide bandwidth switched capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Dual IF Receiver
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD6643
14
VIN+A
NOISE SHAPING
PIPELINE
REQUANTIZER
ADC
VIN–A
VCM
14
VIN+B
NOISE SHAPING
PIPELINE
REQUANTIZER
ADC
VIN–B
REFERENCE
SERIAL PORT
SCLK
SDIO
CSB
NOTES
1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
Figure 1.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6643 supports enhanced SNR per-
formance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution.
The NSR block can be programmed to provide a bandwidth
of either 22% or 33% of the sample clock. For example, with a
sample clock rate of 185 MSPS, the AD6643 can achieve up to
75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and
up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD6643
DCO±
11
D0±
11
D10±
OEB
CLOCK
SYNC
DIVIDER
PDWN
CLK+
CLK–
(continued on Page 3)
www.analog.com

AD6643 Summary of contents

  • Page 1

    ... The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6643 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode. ...

  • Page 2

    ... Changes to Table 4 ............................................................................ 8 Changes to Figure 2 .......................................................................... 9 Change to OEB Pin Description, Table 8 .................................... 12 Changes Figure 5 and Table 9 ....................................................... 13 Changes to Typical Performance Characteristics Conditions Summary .......................................................................................... 15 Added AD6643-200 Throughout ................................................. 15 Changes to Figure 24 and Figure 25 ............................................. 18 Changes to Theory of Operation Section .................................... 19   Voltage Reference ....................................................................... 21   Clock Input Considerations ...................................................... 21   ...

  • Page 3

    ... Data Sheet When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6643 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6643 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required ...

  • Page 4

    ... Full 154 215 Full 172 Full 186 Full 706 855 Full 738 Full 765 Full 90 Full 10 Rev Page Data Sheet AD6643-250 Min Typ Max Unit 11 Bits Guaranteed ±10 mV −5/+3 % FSR ±0.1 ±0.4 LSB ±0.2 ±0.4 LSB ±13 mV −2.5/+3.5 % FSR ± ...

  • Page 5

    ... Full 65.1 25°C 65.3 25°C 65.1 Full 25°C 64.9 25°C −92 25°C −91 Full −80 25°C −88 25°C −88 Full 25°C −84 Rev Page AD6643 AD6643-250 Min Typ Max Unit 66.4 dBFS 66.2 dBFS dBFS 66.1 dBFS 65.9 dBFS 65.3 dBFS 65.6 dBFS 74.8 dBFS 74.5 dBFS dBFS 74.2 dBFS 73.7 dBFS 72.6 dBFS 73 ...

  • Page 6

    ... Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and it is not attenuated internally. DIGITAL SPECIFICATIONS—AD6643-200/AD6643-250 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, default SPI, unless otherwise noted. ...

  • Page 7

    ... Full 1.22 Full 0 Full 45 Full −5 Full Full Full 1.22 Full 0 Full 45 Full −5 Full Full Full 250 Full 150 Full 1.15 Full 1.15 Rev Page AD6643 Typ Max Unit +5 μA +100 μ kΩ 2 μA −45 μA 26 kΩ 2 μ ...

  • Page 8

    ... Conversion rate is the clock rate after the divider. 2 See Figure 2 for timing diagram. 3 Cycles refers to ADC input sample rate cycles. 4 Not shown in timing diagrams. TIMING SPECIFICATIONS—AD6643-200/AD6643-250 Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS See Figure 3 for timing details t SYNC to the rising edge of CLK setup time ...

  • Page 9

    ... N – – – – – B10 B10 B10 N – – – – – 7 AD6643 – – – – – – 6 ...

  • Page 10

    ... AD6643 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND OEB to AGND PDWN to AGND OR+/OR− to AGND D0−/D0+ Through D10−/D10+ to AGND DCO+/DCO− ...

  • Page 11

    ... Channel A/Channel B LVDS Output Data 2—True. Output Channel A/Channel B LVDS Output Data 2—Complement. Output Channel A/Channel B LVDS Output Data 3—True. Output Channel A/Channel B LVDS Output Data 3—Complement. Output Channel A/Channel B LVDS Output Data 4—True. Rev Page AD6643 48 PDWN 47 OEB 46 CSB 45 SCLK 44 ...

  • Page 12

    ... AD6643 Pin No. Mnemonic 26 D4− 30 D5+ 29 D5− 32 D6+ 31 D6− 34 D7+ 33 D7− 36 D8+ 35 D8− 39 D9+ 38 D9− 41 D10+ (MSB) 40 D10− (MSB) 43 OR+ 42 OR− 25 DCO+ 24 DCO− SPI Control 45 SCLK 44 SDIO 46 CSB Output Enable Bar and Power-Down ...

  • Page 13

    ... Channel B LVDS Output 0/Data 0—Complement. The output bit on the rising edge of the data clock output (DCO) from this output is always a Logic 0. Output Channel B LVDS Output 0/Data 0—True. The output bit on the rising edge of the data clock output (DCO) from this output is always a Logic 0. Rev Page AD6643 PDWN 48 47 OEB 46 ...

  • Page 14

    ... AD6643 Pin No. Mnemonic 13 B D1−/D2− D1+/D2 D3−/D4− D3+/D4 D5−/D6− D5+/D6 D7−/D8− D7+/D8 D9−/D10− (MSB D9+/D10+ (MSB 0/D0− (LSB 0/D0+ (LSB D1−/D2− D1+/D2 D3−/D4− D3+/D4 D5−/D6− ...

  • Page 15

    ... IN 0 200MSPS 220.1MHz @ –1dBFS SNR = 65dB (66dBFS) SFDR = 84dBc THIRD HARMONIC SECOND HARMONIC FREQUENCY (MHz) Figure 10. AD6643-200 Single Tone FFT 220.1 MHz IN 0 200MSPS 305.1MHz @ –1dBFS SNR = 64.4dB (65.4dBFS) SFDR = 79dBc THIRD HARMONIC FREQUENCY (MHz) Figure 11 ...

  • Page 16

    ... Figure 14. AD6643-200 Two Tone SFDR/IMD3 vs. Input Amplitude ( 89.12 MHz 92.12 MHz IN1 IN2 SFDR (dBc) –30 –20 – Figure 15. AD6643-200 Two Tone SFDR/IMD3 vs. Input Amplitude ( 175 185 195 ) Figure 16. AD6643-200 Two Tone FFT with f IN –32.5 –21.0 –7.0 ) with Figure 17. AD6643-200 Two Tone FFT with f IN Rev ...

  • Page 17

    ... SFDR, CHANNEL 100 110 120 130 140 150 160 SAMPLE RATE (MSPS) Figure 18. AD6643-200 Single Tone SNR/SFDR vs. Sample Rate (f with f = 90.1 MHz IN 12,000 10,000 8000 6000 4000 2000 OUTPUT CODE Figure 19. AD6643-200 Grounded Input Histogram ...

  • Page 18

    ... AD6643 EQUIVALENT CIRCUITS AVDD VIN Figure 20. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 21. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 22. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ Figure 23. Equivalent SDIO Circuit Figure 24 ...

  • Page 19

    ... Programming and control of the AD6643 are accomplished using a 3-wire SPI-compatible serial interface. ANALOG INPUT CONSIDERATIONS The analog input to the AD6643 is a differential switched capacitor circuit designed for optimum performance in differential signal processing. The clock signal alternatively switches the input between sample mode and hold mode (see Figure 27) ...

  • Page 20

    ... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD6643 (see Figure 28), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 15pF 200Ω ...

  • Page 21

    ... Jitter Considerations section. Figure 33 and Figure 34 show two preferred methods for clocking the AD6643 (at clock rates 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. ...

  • Page 22

    ... ADCs (see www.analog.com). POWER DISSIPATION AND STANDBY MODE As shown in Figure 38, the power dissipated by the AD6643 is proportional to its sample rate. The data in Figure 38 was taken using the same operating conditions as those used for the Typical Performance Characteristics ...

  • Page 23

    ... Timing The AD6643 provides latched data with a pipeline delay of 10 input sample clock cycles (13 input sample clock cycles when NSR is enabled). Data outputs are available one propagation delay (t after the rising edge of the clock signal. ...

  • Page 24

    ... CENTER 0 ADC 0.22 × ADC Figure 39 to Figure 41 show the typical spectrum that can be expected from the AD6643 in the 22% BW mode for three different tuning words. 0 200MSPS 140.1MHz @ –1.6dBFS –20 SNR = 73.6dB (75.2dBFS) SFDR = 86dBc (IN BAND) –40 –60 –80 – ...

  • Page 25

    ... CENTER 0 ADC 0.33 × ADC Figure 42 to Figure 44 show the typical spectrum that can be expected from the AD6643 in the 33% BW mode for three different tuning words. 0 200MSPS 140.1MHz @ –1.6dBFS –20 SNR = 71.3dB (72.9dBFS) SFDR = 86dBc (IN BAND) –40 –60 –80 – ...

  • Page 26

    ... AD6643 CHANNEL/CHIP SYNCHRONIZATION The AD6643 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A ...

  • Page 27

    ... The pins described in Table 12 comprise the physical interface between the user’s programming device and the serial port of the AD6643. Both the SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 28

    ... Table 13 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI (available at www.analog.com). The AD6643 part- specific features are described in the Memory Map Register Description section ...

  • Page 29

    ... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD6643 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 14. Logic Levels An explanation of logic level terminology follows:  ...

  • Page 30

    ... Open Open (global) 0x0B Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-Bit Chip ID[7:0] (AD6643 = 0x84) (default) Speed grade ID Open Open 00 = 250 MSPS 10 = 200 MSPS Open Open Open Open Open Open Open Open External Open ...

  • Page 31

    ... Open Full-scale input voltage selection 01111 = 2.087 V p-p … 00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p User Test Pattern 1[7:0] User Test Pattern 1[15:8] Rev Page AD6643 Default Bit 0 Value Default Notes/ Bit 1 (LSB) (Hex) Comments 0x00 When this register is set, ...

  • Page 32

    ... AD6643 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x1B User Test Pattern 2 LSB (global) 0x1C User Test Pattern 2 MSB (global) 0x1D User Test Pattern 3 LSB (global) 0x1E User Test Pattern 3 MSB (global) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test ...

  • Page 33

    ... For either mode, each step represents 0.5% of the ADC sample rate. For the equations that are used to calculate the tuning word based on the BW mode of operation, see the Noise Shaping Requantizer (NSR) section. Rev Page AD6643 ...

  • Page 34

    ... Decouple the VCM pin to ground with a 0.1 μF capacitor, as shown in Figure 29. For optimal channel-to-channel isolation Ω resistor should be included between the AD6643 VCM pin and the Channel A analog input network connection and between the AD6643 VCM pin and the Channel B analog input network connection ...

  • Page 35

    ... Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board with AD6643-200 Evaluation Board with AD6643-250 Rev Page 0.60 MAX PIN 1 ...

  • Page 36

    ... AD6643 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09638-0-9/11(A) Rev Page Data Sheet ...