AD6643 Analog Devices, AD6643 Datasheet - Page 13

• Manufacturer Part Number: AD6643
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Data Sheet
Table 9. Pin Function Descriptions for the Channel Multiplexed (Even/Odd) LVDS Mode
Pin No.
ADC Power Supplies
ADC Analog
Digital Input
Digital Outputs
10, 19, 28, 37
49, 50, 53, 54, 59,
60, 63, 64
4, 5, 8, 9, 26, 27,
55, 56, 58
0
51
52
62
61
57
1
2
3
7
6
11
12
Mnemonic
DRVDD
AVDD
DNC
AGND, Exposed
Paddle
VIN+A
VIN−A
VIN+B
VIN−B
VCM
CLK+
CLK−
SYNC
ORB+
ORB−
B 0/D0− (LSB)
B 0/D0+ (LSB)
B 0/D0– (LSB)
B 0/D0+ (LSB)
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE
Figure 5. Pin Configuration (Top View), LFCSP Channel Multiplexed (Even/Odd) LVDS
INDICATOR
ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
B D1–/D2–
B D1+/D2+
B D3–/D4–
B D3+/D4+
DRVDD
SYNC
ORB–
ORB+
CLK+
CLK–
PIN 1
DNC
DNC
DNC
DNC
10
11
12
13
14
15
16
Supply
Supply
Ground
Input
Input
Input
Input
Input
Input
Input
Output
Output
1
2
3
4
5
6
7
8
9
Type
Output
Output
Output
Rev. A | Page 13 of 36
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect. Do not connect to these pins.
The exposed thermal paddle on the bottom of the package provides the
analog ground for the part. This exposed paddle must be connected to
ground for proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Digital Synchronization Pin. Slave mode only.
Channel B LVDS Overrange Output—True. The overrange indication is valid on
the rising edge of the DCO.
Channel B LVDS Overrange Output—Complement. The overrange indication
is valid on the rising edge of the DCO.
Channel B LVDS Output 0/Data 0—Complement. The output bit on the rising
edge of the data clock output (DCO) from this output is always a Logic 0.
Channel B LVDS Output 0/Data 0—True. The output bit on the rising edge of
the data clock output (DCO) from this output is always a Logic 0.
MULTIPLEXED
(Not to Scale)
LVDS MODE
(EVEN/ODD)
TOP VIEW
AD6643
CHANNEL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
ORA+
ORA–
A D9+/D10+ (MSB)
A D9–/D10– (MSB)
A D7+/D8+
A D7–/D8–
DRVDD
A D5+/D6+
A D5–/D6–
A D3+/D4+
A D3–/D4–
AD6643