AD6643 Analog Devices, AD6643 Datasheet - Page 14

• Manufacturer Part Number: AD6643
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

AD6643
Pin No.
SPI Control
Output Enable Bar
13
14
15
16
17
18
20
21
22
23
29
30
31
32
33
34
35
36
38
39
40
41
43
42
25
24
45
44
46
and Power-Down
47
48
Mnemonic
B D1−/D2−
B D1+/D2+
B D3−/D4−
B D3+/D4+
B D5−/D6−
B D5+/D6+
B D7−/D8−
B D7+/D8+
B D9−/D10− (MSB)
B D9+/D10+ (MSB)
A 0/D0− (LSB)
A 0/D0+ (LSB)
A D1−/D2−
A D1+/D2+
A D3−/D4−
A D3+/D4+
A D5−/D6−
A D5+/D6+
A D7−/D8−
A D7+/D8+
A D9−/D10− (MSB)
A D9+/D10+ (MSB)
ORA+
ORA−
DCO+
DCO−
SCLK
SDIO
CSB
OEB
PDWN
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input/Output
Input
Input
Input
Rev. A | Page 14 of 36
Channel B LVDS Output Data 9/Data 10—Complement.
Description
Channel B LVDS Output Data 1/Data 2—Complement.
Channel B LVDS Output Data 1/Data 2—True.
Channel B LVDS Output Data 3/Data 4—Complement.
Channel B LVDS Output Data 3/Data 4—True.
Channel B LVDS Output Data 5/Data 6—Complement.
Channel B LVDS Output Data 5/Data 6—True.
Channel B LVDS Output Data 7/Data 8—Complement.
Channel B LVDS Output Data 7/Data 8—True.
Channel B LVDS Output Data 9/Data 10—True.
Channel B LVDS Output 0/Data 1—Complement. The first output bit from this
output is always a Logic 0.
Channel B LVDS Output 0/Data 1—True. The first output bit from this output is
always a Logic 0.
Channel A LVDS Output Data 1/Data 0—Complement.
Channel A LVDS Output Data 1/Data 0—True.
Channel A LVDS Output Data 3/Data 2—Complement.
Channel A LVDS Output Data 3/Data 2—True.
Channel A LVDS Output Data 5/Data 4—Complement.
Channel A LVDS Output Data 5/Data 4—True.
Channel A LVDS Output Data 7/Data 6—Complement.
Channel A LVDS Output Data 7/Data 6—True.
Channel A LVDS Output Data 9/Data 8—Complement.
Channel A LVDS Output Data 9/Data 8—True.
Channel A LVDS Overrange Output—True. The overrange indication is valid on
the rising edge of the DCO.
Channel A LVDS Overrange Output—Complement. The overrange indication
is valid on the rising edge of the DCO.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Serial Clock (SCKL). The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SPI Serial Data Input/Output (SDIO). A dual purpose pin that typically serves as
an input or an output, depending on the instruction being sent and the
relative position in the timing frame.
SPI Chip Select Bar (Active Low). An active low control that gates the read and
write cycles.
Output Enable Bar Input (Active Low).
Power-Down Input (Active High). The operation of this pin depends on the SPI
mode and can be configured as power-down or standby (see Table 14).
Data Sheet