AD6643 Analog Devices, AD6643 Datasheet - Page 2

• Manufacturer Part Number: AD6643
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

AD6643
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings .......................................................... 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
REVISION HISTORY
9/11—Rev. 0 to Rev. A
Added 250 MSPS Speed Grade Throughout................................. 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Changes to Table 4 ............................................................................ 8
Changes to Figure 2 .......................................................................... 9
Change to OEB Pin Description, Table 8 .................................... 12
Changes Figure 5 and Table 9 ....................................................... 13
Changes to Typical Performance Characteristics Conditions
Summary .......................................................................................... 15
Added AD6643-200 Throughout ................................................. 15
Changes to Figure 24 and Figure 25 ............................................. 18
Changes to Theory of Operation Section .................................... 19
ADC DC Specifications ................................................................. 4
ADC AC Specifications ................................................................. 5
Digital Specifications—AD6643-200/AD6643-250 ..................... 6
Switching Specifications ................................................................ 8
Timing Specifications—AD6643-200/AD6643-250 ................ 8
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
ADC Architecture ...................................................................... 19
Analog Input Considerations .................................................... 19
Rev. A | Page 2 of 36
Noise Shaping Requantizer (NSR) ............................................... 24
Channel/Chip Synchronization .................................................... 26
Serial Port Interface (SPI) .............................................................. 27
Memory Map .................................................................................. 29
Applications Information .............................................................. 34
Outline Dimensions ....................................................................... 35
Changes to Timing Section ........................................................... 23
Added ADC Overrange (OR) Section ......................................... 23
Changed Frequency (Hz) to Frequency (MHz) in Figure 39,
Figure 40, and Figure 41 ................................................................ 24
Changed Frequency (Hz) to Frequency (MHz) in Figure 42,
Figure 43, and Figure 44 ................................................................ 25
Changes to Channel/Chip Synchronization Section ................. 26
Changed 0x59 to 0x3E Throughout ............................................. 29
Changes to 0x02, Bits[5:4] and 0x16, Bit 5 in Table 14 ............. 30
Deleted 0x59, Table 14 ................................................................... 32
Deleted SYNC Pin Control (Register 0x59) Section .................. 33
Changes to Ordering Guide .......................................................... 35
4/11—Revision 0: Initial Version
Voltage Reference ....................................................................... 21
Clock Input Considerations ...................................................... 21
Power Dissipation and Standby Mode .................................... 22
Digital Outputs ........................................................................... 23
ADC Overrange (OR) ................................................................ 23
22% BW Mode (>40 MHz at 184.32 MSPS) ........................... 24
33% BW Mode (>60 MHz at 184.32 MSPS) ........................... 25
Configuration Using the SPI ..................................................... 27
Hardware Interface ..................................................................... 27
SPI Accessible Features .............................................................. 28
Reading the Memory Map Register Table ............................... 29
Memory Map Register Table ..................................................... 30
Memory Map Register Description ......................................... 33
Design Guidelines ...................................................................... 34
Ordering Guide .......................................................................... 35
Data Sheet