AD6643 Analog Devices, AD6643 Datasheet - Page 30

• Manufacturer Part Number: AD6643
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

AD6643
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 14 are not currently supported for this device.
Table 14. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0B
Register
Name
SPI port
configuration
(global)
Chip ID
(global)
Chip grade
(global)
Channel
index
(global)
Transfer
(global)
Power
modes (local)
Global clock
(global)
Clock divide
(global)
1
Bit 7
(MSB)
0
Open
Open
Open
Open
Open
Open
Bit 6
LSB
first
Open
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
External
power-
down pin
function
(local)
0 = power-
down
1 = standby
Open
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
001 = 1 input clock cycle
Speed grade ID
00 = 250 MSPS
10 = 200 MSPS
Input clock divider
000 = no delay
phase adjust
Bit 4
1
Open
Open
Open
Open
8-Bit Chip ID[7:0]
(AD6643 = 0x84)
Rev. A | Page 30 of 36
(default)
Bit 3
1
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
LSB first
Open
Bit 1
Open
ADC B
(default)
Open
00 = normal operation
01 = full power-down
Internal power-down
11 = reserved
10 = standby
mode (local)
0
Bit 0
(LSB)
Open
ADC A
(default)
Transfer
Duty cycle
stabilizer
(default)
0x18
Default
Value
(Hex)
0x84
0x03
0x00
0x00
0x01
0x00
Data Sheet
Default Notes/
Comments
The nibbles
are mirrored so
LSB-first mode or
MSB-first mode
registers
correctly,
regardless of shift
mode
Read only
Speed grade ID
used to
differentiate
devices; read
only
Bits are set
to determine
which device on
the chip receives
the next write
command;
applies to local
registers only
Synchronously
transfers data
from the master
shift register to
the slave
Determines
various generic
modes of chip
operation
Clock divide
values other
than 000 auto-
matically cause
the duty cycle
stabilizer to
become active