AD6649

Manufacturer Part NumberAD6649
DescriptionIF Diversity Receiver
ManufacturerAnalog Devices
AD6649 datasheet
 
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Data Sheet
FEATURES
SNR = 73.4 dBFS in a 95 MHz bandwidth at
185 MHz A
and 245.76 MSPS
IN
SFDR = 85 dBc at 185 MHz A
and 250 MSPS
IN
Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS
A
and 250 MSPS
IN
Total power consumption: 1 W with fixed-frequency NCO,
95 MHz FIR filter
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Integrated dual-channel ADC
Sample rates of up to 250 MSPS
IF sampling frequencies to 400 MHz
Internal ADC voltage reference
Flexible input range
1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital processor
32-bit complex numerically controlled oscillator (NCO)
FIR filter with 2 modes
Real output from an f
/4 output NCO
S
Amplitude detect bits for efficient AGC implementation
Energy saving power-down modes
Decimated, interleaved real LVDS data outputs
AVDD
FDA
THRESHOLD DETECT
VIN+A
ADC
VIN–A
DC
CORRECTION
REFERENCE
DC
CORRECTION
VIN–B
ADC
VIN+B
THRESHOLD DETECT
AGND
FDB
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications
GENERAL DESCRIPTION
The AD6649 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital
downconverter (DDC). The AD6649 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
SELECTABLE
I
FIR
FILTER
Q
SELECTABLE
FIR
FILTER
f
32-BIT
/4
S
TUNING NCO
NCO
Q
SELECTABLE
FIR
FILTER
I
SELECTABLE
FIR
FILTER
PDWN
OEB
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
IF Diversity Receiver
AD6649
DRVDD
AD6649
OR+
OR–
DIGITAL
D13+/D13–
INTERLEAVING
D0+/D0–
CLK+
DIVIDE 1
TO 8
CLK–
DUTY
DCO+
DCO
CYCLE
GENERATION
STABILIZER
DCO–
MULTICHIP
SYNC
SYNC
PROGRAMMING DATA
SPI
SDIO SCLK CSB
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.

AD6649 Summary of contents

  • Page 1

    ... CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applications GENERAL DESCRIPTION The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC). The AD6649 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired ...

  • Page 2

    ... AD6649 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ................................................................. 4 ADC AC Specifications ................................................................. 5 Digital Specifications ..................................................................... 6 Switching Specifications ................................................................ 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 13 Equivalent Circuits ......................................................................... 16 Theory of Operation ...

  • Page 3

    ... S Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface. The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Integrated dual, 14-bit, 250 MSPS ADCs. ...

  • Page 4

    ... AD6649 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, duty cycle stabilizer (DCS) enabled, NCO enabled, FIR filter enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error MATCHING CHARACTERISTIC Offset Error ...

  • Page 5

    ... Full 25°C 25°C 25°C 25°C 25°C 80 Full 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C Full 25°C Rev Page AD6649 Typ Max Unit 74.5 dBFS 74.2 dBFS 73.9 dBFS 73.4 dBFS dBFS 72.9 dBFS 73.4 dBFS 73.0 dBFS 72.3 dBFS 71.7 dBFS dBFS 71.0 dBFS − ...

  • Page 6

    ... AD6649 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current ...

  • Page 7

    ... NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters section for more details. 2 Pull-up. 3 Pull-down. Temperature Full Full Full Full Full Full Full Full Full Full Rev Page AD6649 Min Typ Max Unit 26 kΩ 1.79 V 1.75 V 0.2 V 0.05 V 250 ...

  • Page 8

    ... AD6649 SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate 1 Conversion Rate CLK Period—Divide-by-1 Mode (t ) CLK CLK Pulse Width High ( Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-3 Through Divide-by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS (DATA, OR) ...

  • Page 9

    ... CHA2 CHB2 CHA3 CHB3 Figure 2. Interleaved LVDS Mode Data Output Timing t t SSYNC HSYNC Figure 3. SYNC Timing Inputs Rev Page Min Typ 0.3 0 CHA4 CHB4 CHA5 CHB5 CHA6 AD6649 Max Unit CHB6 ...

  • Page 10

    ... AD6649 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND OEB to AGND PDWN to AGND D0−/D0+ through D13−/D13+ ...

  • Page 11

    ... Channel A/Channel B LVDS Output Data 1—True. Output Channel A/Channel B LVDS Output Data 1—Complement. Output Channel A/Channel B LVDS Output Data 2—True. Output Channel A/Channel B LVDS Output Data 2—Complement. Output Channel A/Channel B LVDS Output Data 3—True. Rev Page AD6649 48 PDWN 47 OEB 46 CSB 45 SCLK 44 ...

  • Page 12

    ... AD6649 Pin No. Mnemonic 15 D3− 18 D4+ 17 D4− 21 D5+ 20 D5− 23 D6+ 22 D6− 27 D7+ 26 D7− 30 D8+ 29 D8− 32 D9+ 31 D9− 34 D10+ 33 D10− 36 D11+ 35 D11− 39 D12+ 38 D12− 41 D13+ (MSB) 40 D13− (MSB) 43 OR+ 42 OR− 25 DCO+ 24 DCO− ...

  • Page 13

    ... THIRD HARMONIC –100 –120 –140 100 110 FREQUENCY (MHz) Figure 9. AD6649 Single-Tone FFT with f = 220.1 MHz 250MSPS 305.1MHz @ –1.0dBFS IN –20 SNR = 68.5dB (71.0dBFS) SFDR = 83.5dBc (IN-BAND) –40 SECOND HARMONIC –60 THIRD HARMONIC – ...

  • Page 14

    ... INPUT AMPLITUDE (dBFS) Figure 13. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (A with f = 89.12 MHz 92.12 MHz, f IN1 IN2 –20 –40 –60 –80 –100 –120 ) Figure 14. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN 350 400 450 ) Figure 15. AD6649 Two-Tone FFT with f IN –32.5 –21.0 –9 250 MSPS S Rev ...

  • Page 15

    ... Data Sheet 100 95 90 SFDR CHANNEL A (dBc) 85 SFDR CHANNEL B (dBc) SNR CHANNEL A (dBFS) SNR CHANNEL B (dBFS SAMPLE RATE (MSPS) Figure 17. AD6649 Single-Tone SNR/SFDR vs. Sample Rate ( 90.1 MHz IN 6000 5000 4000 3000 2000 1000 0 ) with Figure 18. AD6649 Grounded Input Histogram S Rev Page AD6649 1 ...

  • Page 16

    ... AD6649 EQUIVALENT CIRCUITS AVDD VIN Figure 19. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 20. Equivalent Clock Input Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 21. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ Figure 22. Equivalent SDIO Circuit ...

  • Page 17

    ... VIN+ and VIN− should be matched, and the inputs should be differentially balanced. Input Common Mode The analog inputs of the AD6649 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V 0 recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin ...

  • Page 18

    ... ADC. The output common-mode voltage of the ADA4930-2 is easily set with the VCM pin of the AD6649 (see Figure 27), and the driver can be configured in a Sallen-Key filter topology to provide band-limiting of the input signal. 15pF 200Ω ...

  • Page 19

    ... Jitter Considerations section. Figure 32 and Figure 33 show two preferable methods for clocking the AD6649 (at clock rates 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. ...

  • Page 20

    ... Jitter, for more information about jitter performance as it relates to ADCs. POWER DISSIPATION AND STANDBY MODE As shown in Figure 37, the power dissipated by the AD6649 is proportional to its sample rate. The data in Figure 37 was taken using the same operating conditions as those used for the Typical Performance Characteristics ...

  • Page 21

    ... VIN+ − VIN– >+0.875 Timing The AD6649 provides latched data with a pipeline delay input sample clock cycles, depending on the mode of operation. Data outputs are available one propagation delay (t rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6649 ...

  • Page 22

    ... Figure 39. Example AD6649 95 MHz Bandwidth Input Signal Tuned to DC Output Using the NCO (NCO Frequency = 61.44 MHz) Bandwidth at 245.76 MSPS 95 MHz 99.5 MHz 0 Figure 40. Example AD6649 95 MHz Bandwidth Output Signal Tuned to f Rev Page Data Sheet /4 NCO is provided to translate the filtered allow a real output. The f S REAL ADC INPUT – ...

  • Page 23

    ... AD6649 ADC clock rate in hertz. CLK NCO SYNCHRONIZATION The AD6649 NCOs within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 0 and Bit 1 of Register 0x58 allow the NCO to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written ...

  • Page 24

    ... C23 0.9171314 FIR SYNCHRONIZATION The AD6649 filters within a single part or across multiple parts can be synchronized using the external SYNC input. The filters can be configured to be resynchronized on every SYNC signal or only on the first SYNC signal after the SPI control register is written. ...

  • Page 25

    ... The final NCO provides a means to move this complex output signal away from dc so that a real output can be provided from the AD6649. The output NCO translates the output from frequency equal to the output frequency divided ...

  • Page 26

    ... ADC clock cycles. An overrange at the input is indicated by this bit 7 clock cycles after it occurs. GAIN SWITCHING The AD6649 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging amplifiers are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed ...

  • Page 27

    ... Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD6649 ADC sample rate in hertz. CLK DC Correction Readback The current dc correction value can be read back in Register 0x41 and Register 0x42 for each channel. The dc correction value is a 16-bit value that can span the entire input range of the ADC ...

  • Page 28

    ... AD6649 CHANNEL/CHIP SYNCHRONIZATION The AD6649 has a SYNC input that allows the user flexible syn- chronization options for synchronizing the internal blocks. The SYNC feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider, NCO, FIR filters, and the output f ...

  • Page 29

    ... ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6649 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. Rev Page ...

  • Page 30

    ... SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD6649 part-specific features are described in the Memory Map Register Description section. Table 14. Features Accessible Using the SPI Feature Name Mode ...

  • Page 31

    ... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD6649 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 15. Logic Levels An explanation of logic level terminology follows: • ...

  • Page 32

    ... Open Open (global) 0x0B Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0] (AD6649 = 0xA1) (default) Speed grade ID Open Open 00 = 250 MSPS Open Open Open Open Open Open Open Open External Open Open Open ...

  • Page 33

    ... V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p User Test Pattern 1[7:0] User Test Pattern 1[15:8] User Test Pattern 2[7:0] User Test Pattern 2[15:8] User Test Pattern 3[7:0] User Test Pattern 3[15:8] Rev Page AD6649 Default Default Value Notes/ Bit 0 Bit 1 (LSB) (Hex) Comments 0x00 When this ...

  • Page 34

    ... AD6649 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x3A Sync control Open Open (global) Digital Feature Control Registers 0x40 ...

  • Page 35

    ... NCO phase value[15:8] NCO phase value[7:0] FIR next FIR Sync Reserved Reserved sync only Enable Open Open Open Open Open Open Open Open Rev Page AD6649 Default Default Value Notes/ Bit 0 Bit 1 (LSB) (Hex) Comments NCO32 1 0x51 phase dither enable 0x40 ...

  • Page 36

    ... Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD6649 ADC sample rate in hertz. CLK Bit 1—DC Correction Enable Setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path ...

  • Page 37

    ... NCO_FREQ is a 32-bit twos complement number representing the NCO frequency register the desired carrier frequency in hertz the AD6649 ADC clock rate in hertz. CLK NCO Phase Offset (Register 0x56 and Register 0x57) Register 0x56, Bits[7:0]—NCO Phase Value[15:8] Register 0x57, Bits[7:0]—NCO Phase Value[7:0] ...

  • Page 38

    ... AD6649 NCO/FIR SYNC Pin Control (Register 0x59) Bits[7:2]—Reserved Bit 1—SYNC Pin Sensitivity If Bit 1 is set the SYNC input responds to a level. If this bit is set low, the SYNC input responds to the edge (rising or falling) set in Bit 0 of Address 0x59. Bit 0—SYNC Pin Edge Sensitivity If Bit 1 is set high, setting Bit causes the SYNC input to respond to a falling edge ...

  • Page 39

    ... The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 28. For optimal channel-to-channel isolation Ω resistor should be included between the AD6649 VCM pin and the Channel A analog input network connection and between the AD6649 VCM pin and the Channel B analog input network connection ...

  • Page 40

    ... Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ × Body, Very Thin Quad (CP-64-4) Dimensions shown in millimeters Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board with AD6649 D09635-0-9/11(A) Rev Page 0.60 MAX PIN 1 INDICATOR 64 ...