AD6649 Analog Devices, AD6649 Datasheet - Page 20

• Manufacturer Part Number: AD6649
• Description: IF Diversity Receiver
• Manufacturer: Analog Devices

AD6649
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD6649 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD6649.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 µs to 5 µs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time period that
the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (f
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 36.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD6649.
Power supplies for clock drivers should be separated from the
SNR
80
75
70
65
60
55
50
Figure 36. SNR (95 MHz BW) vs. Input Frequency and Jitter
1
HF
= −10 log[(2π × f
IN
) due to jitter (t
0.05ps
0.20ps
0.50ps
1.00ps
1.50ps
MEASURED
10
INPUT FREQUENCY (MHz)
IN
J
) can be calculated by
× t
JRMS
)
2
100
+ 10
(
/
SNR
LF
/
10
)
]
1000
Rev. A | Page 20 of 40
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the
and ADC System Performance, and the
Note, Sampled Systems and the Effects of Clock Phase Noise and
Jitter, for more information about jitter performance as it relates
to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 37, the power dissipated by the AD6649 is
proportional to its sample rate. The data in Figure 37 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics.
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD6649 is placed in power-down
mode. In this state, the ADC typically dissipates 10 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD6649 to its
normal operating mode. Note that PDWN is referenced to the
digital output driver supply (DRVDD) and should not exceed
that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the
to High Speed ADCs via SPI, for additional details.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
40
TOTAL POWER
Figure 37. AD6649 Power and Current vs. Sample Rate
I
DRVDD
60
I
AVDD
AN-501 Application
80
ENCODE FREQUENCY (MSPS)
100
120
AN-877 Application
140
Note, Aperture Uncertainty
160
AN-756 Application
180
200
Data Sheet
Note, Interfacing
220
250
0.5
0.4
0.3
0.2
0.1
0