AD6649 Analog Devices, AD6649 Datasheet - Page 6

• Manufacturer Part Number: AD6649
• Description: IF Diversity Receiver
• Manufacturer: Analog Devices

AD6649
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
SYNC INPUT
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK)
LOGIC INPUT/OUTPUT (SDIO)
LOGIC INPUTS (OEB, PDWN)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
Input Capacitance
Input Resistance
High Level Input Current
Low Level Input Current
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
2
3
3
2
Rev. A | Page 6 of 40
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1
1.0 V internal reference,
0.3
+10
8
1.2
−5
12
1.22
−5
1.22
45
1.22
45
1.22
45
−5
Min
AGND
0.9
−22
AGND
AGND
−5
0
−80
0
−5
0
−5
0
CMOS/LVDS/LVPECL
CMOS/LVDS
Typ
0.9
4
10
0.9
1
16
26
2
26
2
26
5
Data Sheet
Max
3.6
AVDD
1.4
+22
−10
12
AVDD
AVDD
0.6
+5
+5
20
2.1
0.6
+5
−45
2.1
0.6
70
+5
2.1
0.6
70
+5
2.1
0.6
70
+5
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
V
V
µA
µA
pF
kΩ
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA