AD6649 Analog Devices, AD6649 Datasheet - Page 9

• Manufacturer Part Number: AD6649
• Description: IF Diversity Receiver
• Manufacturer: Analog Devices

Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
D0+ TO D13+
D0– TO D13–
DCO+
DCO–
CLK+
CLK–
CHA0
CHB0
t
PD
t
CH
Conditions
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
CHA1
SYNC
CLK+
CHB1
Figure 2. Interleaved LVDS Mode Data Output Timing
CHA2
t
t
SSYNC
CLK
Figure 3. SYNC Timing Inputs
CHB2
Rev. A | Page 9 of 40
t
DCO
t
CHA3
HSYNC
t
SKEW
CHB3
CHA4
CHB4
CHA5
CHB5
Min
2
2
40
2
2
10
10
10
10
CHA6
Typ
0.3
0.4
CHB6
Max
AD6649
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns