AD9434 Analog Devices, AD9434 Datasheet - Page 20

• Manufacturer Part Number: AD9434
• Description: 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9434

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 500MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.5 V p-p,Bip 0.75V
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9434
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9434 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased at ~0.9 V
internally and require no additional bias. If the clock signal is
dc-coupled, then the common-mode voltage should remain
within a range of 0.9 V.
Figure 44 shows one preferred method for clocking the AD9434.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9434 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9434 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 45. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515
performance.
CLOCK
INPUT
Figure 44. Transformer-Coupled Differential Clock
50Ω
0.1µF
family of clock drivers offers excellent jitter
100Ω
ADT1–1WT, 1:1Z
MINI-CIRCUITS
XFMR
0.1µF
ANALOG INPUT
ANALOG INPUT
0.1µF
0.1µF
SCHOTTKY
HSM2812
DIODES:
C
D
Figure 43. Differential Input Configuration Using the
0.1µF
0.1µF
R
D
CLK+
CLK–
AD9434
0Ω
0Ω
ADC
R
G
16
1
2
3
4
5
V
AD8352
CC
Rev. A | Page 20 of 28
8, 13
14
0.1µF
0.1µF
11
10
0.1µF
0.1µF
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate,
and bypass the CLK− pin to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor (see Figure 47).
1
1
CLOCK
1
50Ω RESISTORS ARE OPTIONAL.
50Ω RESISTORS ARE OPTIONAL.
INPUT
50Ω RESISTOR IS OPTIONAL.
CLOCK
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
INPUT
200Ω
200Ω
Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50Ω
50Ω
1
1
50Ω
R
R
0.1µF
C
0.1µF
1
AD8352
Figure 46. Differential LVDS Sample Clock
Figure 45. Differential PECL Sample Clock
0.1µF
0.1µF
50Ω
0.1µF
0.1µF
50Ω
V
CC
1kΩ
1kΩ
1
1
AD9434
CLK
CLK
CLK
CLK
VIN+
VIN– CML
PECL DRIVER
LVDS DRIVER
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
AD951x
CMOS DRIVER
240Ω
0.1µF
OPTIONAL
240Ω
100Ω
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
AD9434
AD9434
AD9434
ADC
ADC
ADC