AD9484

Manufacturer Part NumberAD9484
Description8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9484 datasheet
 


Specifications of AD9484

Resolution (bits)8bit# Chan1
Sample Rate500MSPSInterfacePar
Analog Input TypeDiff-BipAin Range1.5 V p-p,Bip 0.75V
Adc ArchitecturePipelinedPkg TypeCSP
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FEATURES
SNR = 47 dBFS at f
up to 250 MHz at 500 MSPS
IN
ENOB of 7.5 bits at f
up to 250 MHz at 500 MSPS (−1.0 dBFS)
IN
SFDR = 79 dBc at f
up to 250 MHz at 500 MSPS (−1.0 dBFS)
IN
Integrated input buffer
Excellent linearity
DNL = ±0.1 LSB typical
INL = ±0.1 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation
670 mW at 500 MSPS—LVDS SDR output
Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Low cost digital oscilloscopes
Satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The
AD9484
is an 8-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS conver-
sion rate and is optimized for outstanding dynamic performance
in wideband carrier and broadband systems. All necessary
functions, including a sample-and-hold and voltage reference,
are included on the chip to provide a complete signal conversion
solution. The VREF pin can be used to monitor the internal
reference or provide an external voltage reference (external
reference mode must be enabled through the SPI port).
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is available
for proper output data timing.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
8-Bit, 500 MSPS,
1.8 V Analog-to-Digital Converter
FUNCTIONAL BLOCK DIAGRAM
VREF
PWDN
REFERENCE
CML
VIN+
TRACK-AND-HOLD
VIN–
ADC
CORE
CLK+
CLOCK
MANAGEMENT
CLK–
SERIAL PORT
SCLK/DFS
SDIO
Figure 1.
Fabricated on an advanced BiCMOS process, the AD9484 is availa-
ble in a 56-lead LFCSP, and is specified over the industrial
temperature range (−40°C to +85°C). This product is protected
by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
High Performance.
Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input.
2.
Ease of Use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 1.8 V supply simplifies system power supply design.
3.
Serial Port Control.
Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD9484
AGND
AVDD
AD9484
DRVDD
DRGND
8
OUTPUT
8
STAGING
D7± TO D0±
LVDS
OR+
OR–
DCO+
DCO–
CSB
www.analog.com

AD9484 Summary of contents

  • Page 1

    ... CLOCK MANAGEMENT CLK– SERIAL PORT SCLK/DFS SDIO Figure 1. Fabricated on an advanced BiCMOS process, the AD9484 is availa- ble in a 56-lead LFCSP, and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. High Performance. ...

  • Page 2

    ... Clock Input Considerations ...................................................... 15   Power Dissipation and Power-Down Mode ........................... 16   Digital Outputs ........................................................................... 16   Timing ......................................................................................... 17   VREF ............................................................................................ 17   AD9484 Configuration Using the SPI ..................................... 18   Hardware Interface ..................................................................... 18   Configuration Without the SPI ................................................ 18   Memory Map .................................................................................. 20   Reading the Memory Map Table .............................................. 20   Reserved Locations .................................................................... 20   ...

  • Page 3

    ... The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the 3 I and I are measured with a −1 dBFS, 10.3 MHz sine input at a rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9484. = +85° −1.0 dBFS, full scale = 1.5 V, unless otherwise noted. MAX IN Temp Min Full 25° ...

  • Page 4

    ... AD9484 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table Parameter SNR f = 30.3 MHz 70.3 MHz 100.3 MHz 250.3 MHz 450.3 MHz IN SINAD f = 30.3 MHz 70.3 MHz 100.3 MHz 250.3 MHz 450.3 MHz IN EFFECTIVE NUMBER OF BITS (ENOB ...

  • Page 5

    ... Full 0.2 Full −1.8 Full −10 Full −10 Full 8 Full Full 0.8 × DRVDD Full Full Full Full Full Full Full 247 Full 1.125 Rev Page AD9484 Typ Max Unit CMOS/LVDS/LVPECL 0.9 V 1.8 V p-p −0.2 V p-p +10 μA +10 μ kΩ 0.2 × DRVDD V 0 μA − ...

  • Page 6

    ... AD9484 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 −40°C, T MIN Table 4. Parameter Maximum Conversion Rate Minimum Conversion Rate 1 CLK+ Pulse Width High ( CLK+ Pulse Width Low ( Output (LVDS—SDR) Data Propagation Delay ( Rise Time (t ) (20% to 80%) R Fall Time (t ) (20% to 80%) ...

  • Page 7

    ... JA JC Airflow increases heat dissipation, effectively reducing θ addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θ ESD CAUTION Rev Page AD9484 θ θ Unit JA JC 23.7 1.7 °C ...

  • Page 8

    ... D2+ 11 D3− 12 D3+ 13 D4− DNC 1 PIN 1 INDICATOR DNC 2 D0– 3 D0+ 4 D1– 5 D1+ 6 AD9484 DRVDD 7 TOP VIEW DRGND 8 (Not to Scale) D2– 9 D2+ 10 D3– 11 D3+ 12 PIN 0 (EXPOSED PADDLE) = AGND D4– 13 D4+ 14 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. ...

  • Page 9

    ... D7− 20 D7+ 21 OR− 22 OR+ 1 Tie AGND and DRGND to a common quiet ground plane. Description D4 True Output. D5 Complement Output. D5 True Output. D6 Complement Output. D6 True Output. D7 Complement Output (MSB). D7 True Output (MSB). Overrange Complement Output. Overrange True Output. Rev Page AD9484 ...

  • Page 10

    ... AD9484 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate 500MSPS –10 30.3MHz AT –1.0dBFS SNR: 46.0dB ENOB: 7.5 BITS –20 SFDR: 82dBc –30 –40 –50 –60 –70 –80 –90 –100 100 120 140 160 180 FREQUENCY (MHz) Figure 4. 64k Point Single-Tone FFT; 500 MSPS, 30.3 MHz ...

  • Page 11

    ... BINS Figure 14. Grounded Input Histogram, 500 MSPS 500MSPS 119.5MHz AT –7.0dBFS 122.5MHz AT –7.0dBFS SFDR: 77dBc 100 120 140 160 180 200 220 240 FREQUENCY (MHz) Figure 15. 64k Point, Two-Tone FFT; 500 MSPS, 119.2 MHz, 122.5 MHz AD9484 256 ...

  • Page 12

    ... AD9484 100 IMD3 (dBFS SFDR (dBFS SFDR (dBc –90 –80 –70 –60 –50 –40 AMPLITUDE (dBFS) Figure 16. Two-Tone SFDR vs. Input Amplitude; 500 MSPS, 119.5 MHz, 122.5 MHz 90 SFDR (dBc SNR (dBFS 1.5 1.6 1.7 1.8 V (V) CM Figure 17. SNR/SFDR vs. Common-Mode Voltage; 500 MSPS, AIN = 140 ...

  • Page 13

    ... V– Dx– Dx+ V– V+ AVDD 20kΩ (00) (01) VREF (10) NOT USED (11) SPI CTRL V SELECT REF 00 = INTERNAL V REF 01 = IMPORT V REF 10 = EXPORT V REF 11 = NOT USED Figure 26. Equivalent VREF Input/Output Circuit DRVDD DRVDD 30kΩ 350Ω Figure 27. Equivalent SDIO Input Circuit AD9484 CTRL ...

  • Page 14

    ... During power-down, the output buffers enter a high impedance state. ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9484 is a differential buffer. For best dynamic performance, match the source impedances driving VIN+ and VIN− such that common-mode settling errors are symmetrical ...

  • Page 15

    ... AD9484 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9484 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. ...

  • Page 16

    ... CLK– 0.1µF POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 18, the power dissipated by the AD9484 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. ...

  • Page 17

    ... MSPS, the AD9484 assumes the standby mode. 0 100 TIME (ps) VREF The AD9484 VREF pin (Pin 31) allows the user to monitor the on-board voltage reference, or provide an external reference (requires configuration through the SPI). The three optional settings are internal V export V to this pin. VREF is internally compensated and additional loading may impact performance ...

  • Page 18

    ... The pins described in Table 8 comprise the physical interface between the programming device of the user and the serial port of the AD9484. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirec- tional, functioning as an input during the write phase and as an output during readback ...

  • Page 19

    ... Figure 39) Offset Binary Output Mode, D7± to D0± 0000 0000 0000 0000 1000 0000 1111 1111 1111 1111 Rev Page AD9484 Twos Complement Mode, D7± to D0± 1000 0000 1000 0000 0000 0000 0111 1111 0111 1111 OR± ...

  • Page 20

    ... AD9484 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table (see Table 12) has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer register map (Address 0xFF), and ADC functions register map (Address 0x08 to Address 0x2A) ...

  • Page 21

    ... Output clock delay: 0x00 0000 = 0 0001 = −1/10 0010 = −2/10 0011 = −3/10 0100 = reserved 0101 = +5/10 0110 = +4/10 0111 = +3/10 1000 = +2/10 1001 = +1/10 AD9484 Default Notes/ Comments Device offset trim: codes are relative to the output resolution. When set, the test data is placed on the output pins in place of normal data ...

  • Page 22

    ... AD9484 Addr. Bit 7 (Hex) Register Name (MSB) 18 FLEX_VREF VREF select 00 = internal V (20 kΩ pull-down import V (0. 0 VREF pin export V (from internal reference not used 19 USER_PATT1_LSB B7 1A USER_PATT1_MSB B7 1B USER_PATT2_LSB B7 1C USER_PATT2_MSB B7 2A OVR_CONFIG 0 2C Input coupling don’t care. ...

  • Page 23

    ... Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page 0.30 0.23 0. EXPOSED 5.25 PAD 5. 0.25 MIN BOTTOM VIEW 6.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-56-5 CP-56-5 AD9484 ...

  • Page 24

    ... AD9484 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09615-0-6/11(A) Rev Page ...