AD9613 Analog Devices, AD9613 Datasheet
AD9613
Specifications of AD9613
Related parts for AD9613
AD9613 Summary of contents
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... GENERAL DESCRIPTION The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds 250 MSPS. The AD9613 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic ...
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... Changes to Bit 0—Master Sync Buffer Enable Section ............. 34 Deleted SYNC Pin Control (Register 0x59) Section.................. 34 5/11—Rev Rev. A Changes to Table 2, AD9613-170: Worst Second or Third Harmonic and Worst Other (Harmonic or Spur) Max Values and Spurious Free Dynamic Range Min Value .............................4 4/11—Revision 0: Initial Version Rev ...
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... AD9613 Unit Bits mV %FSR LSB LSB LSB LSB mV %FSR ppm/°C ppm/°C LSB rms V p-p pF kΩ ...
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... Full 25°C −80 25°C 94 25°C 92 Full 78 80 25°C 87 25°C 89 Full 25°C 83 25°C −97 25°C −96 Full −78 25°C −97 25°C −91 Full 25°C −93 Rev Page Data Sheet AD9613-250 Typ Max Min Typ Max 70.1 70.0 70.0 69.8 69.8 69.6 69.5 69.2 67.8 69.3 69.0 69.1 69.0 69.0 68.8 68.8 68.6 68.5 68.2 66.5 68.3 68.0 11.2 11.2 11.2 11.1 11.1 11.1 11.1 11 ...
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... Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally. AD9613-170 AD9613-210 Temp Min Typ Max Min 25°C 88 Full 95 25°C 400 25°C 1000 Rev Page AD9613 AD9613-250 Typ Max Min Typ Max 400 400 1000 1000 Unit dBc dB MHz ...
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... AD9613 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range ...
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... Reduced Swing Mode OS 1 Pull up. 2 Pull down. Temp Min Full 1.22 Full 0 Full 45 Full −5 Full Full Full 250 Full 1.15 Full 150 Full 1.15 Rev Page AD9613 Typ Max Unit 2 μA +5 μA 26 kΩ 350 450 mV 1.22 1.35 V 200 280 mV 1.22 1.35 ...
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... Full 40 170 40 Full 5.8 4.8 Full 2.61 2.9 3.19 2.16 Full 2.76 2.9 3.05 2.28 Full 0.8 0.8 Full 1.0 Full 0.1 Full 4.8 Full 5.5 Full 0.3 0.7 1.1 0.3 Full 10 Full 1.0 Full 0.1 Full 10 Full 250 Full 3 Rev Page Data Sheet AD9613-250 Typ Max Min Typ Max Unit 625 625 MHz 210 40 250 MSPS 4 ns 2.4 2.64 1.8 2.0 2.2 ns 2.4 2.52 1.9 2.0 2.1 ns 0.8 ns 1.0 1.0 ns 0.1 0.1 ps rms 4.8 4.8 ns 5.5 5.5 ns 0.7 1.1 0.3 0.7 1.1 ...
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... Time required for the SDIO pin to switch from an input to an output EN_SDIO relative to the SCLK falling edge (not shown in Figure 58) t Time required for the SDIO pin to switch from an output to an input DIS_SDIO relative to the SCLK rising edge (not shown in Figure 58) Rev Page AD9613 Min Typ Max Unit 0.3 ns 0.4 ...
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... AD9613 Timing Diagrams VIN CLK+ CLK– DCO– DCO+ PARALLEL INTERLEAVED D0± (LSB CHANNEL A AND . CHANNEL B D11± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE (LSB CHANNEL A . D10±/D11± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE (LSB CHANNEL B . D10± ...
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... ESD CAUTION Rev Page specified for a 4-layer PCB with solid ground addition, metal in direct contact with the Airflow Velocity (m/sec) θ θ 26.8 1.14 1.0 21.6 2.0 20.2 AD9613 1, 4 θ Unit JB 10.4 °C/W °C/W °C/W ...
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... VCM 61 VIN−B 62 VIN+B Digital Input 3 SYNC PIN 1 CLK+ 1 CLK– 2 SYNC 3 DNC 4 DNC 5 DNC 6 AD9613 DNC 7 PARALLEL LVDS DNC 8 TOP VIEW DNC 9 (Not to Scale) DRVDD 10 DNC 11 DNC D1– 15 D1+ 16 PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION ...
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... SPI Serial Data I/O. Input SPI Chip Select (Active Low). Input/Output Output Enable Bar Input (Active Low). Input/Output Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14. Rev Page AD9613 ...
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... VCM 1 CLK+ 2 CLK− Digital Input 3 SYNC Digital Outputs 7 ORB+ 6 ORB− PIN 1 CLK+ 1 CLK– 2 SYNC 3 DNC 4 DNC 5 AD9613 ORB– 6 CHANNEL ORB+ 7 MULTIPLEXED DNC 8 (EVEN/ODD) DNC 9 LVDS 10 TOP VIEW 11 (Not to Scale Type Description Supply Digital Output Driver Supply (1.8 V Nominal). ...
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... SPI Serial Data I/O. Input SPI Chip Select (Active Low). Input Output Enable Bar Input (Active Low). Input Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14. Rev Page AD9613 ...
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... MHz Figure 10. AD9613-170 Single-Tone SNR/SFDR vs. Input Frequency (f IN 170MSPS 305.1MHz @ –1dBFS SNR = 67dB (68dBFS) SFDR = 79dBc SECOND HARMONIC 305.1 MHz Figure 11. AD9613-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN Rev Page 120 SFDR (dBFS) 100 80 SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) ...
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... FREQUENCY (MHz) Figure 14. AD9613-170 Two-Tone FFT with f IN1 f = 170 MSPS S –32.5 –21.0 –7.0 Figure 15. AD9613-170 Single-Tone SNR/SFDR vs. Sample Rate (f = 170 MSPS 89.12 92.12 MHz, IN2 184.12 187.12 MHz, IN2 Rev Page 100 95 90 ...
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... MHz Figure 21. AD9613-210 Single-Tone SNR/SFDR vs. Input Frequency (f IN –100 –120 100 = 305.1 MHz Figure 22. AD9613-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN SNR (dBc) –100 –120 –30 –20 – with IN Input Amplitude (A Rev Page SFDR (dBc) ...
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... Figure 25. AD9613-210 Two-Tone FFT with f IN1 f = 210 MSPS S 100 100 120 140 SAMPLE RATE (MSPS) Figure 26. AD9613-210 Single-Tone SNR/SFDR vs. Sample Rate (f with MHz 100 = 89.12 92.12 MHz, IN2 100 = 184.12 187.12 MHz, IN2 SNR, CHANNEL B SFDR, CHANNEL B ...
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... FREQUENCY (MHz) Figure 32. AD9613-250 Single-Tone SNR/SFDR vs. Input Frequency (f SECOND HARMONIC 80 90 100 110 120 = 305.1 MHz Figure 33. AD9613-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN SNR (dBc) –30 –20 – with IN Input Amplitude (A 200 220 240 260 Figure 35 ...
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... SAMPLE RATE (MSPS) Figure 37. AD9613-250 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 90.1 MHz 100 110 120 = 184.12 187.12 MHz, IN2 SNR, CHANNEL B SFDR, CHANNEL B SNR, CHANNEL A SFDR, CHANNEL A 180 200 220 240 ...
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... AD9613 EQUIVALENT CIRCUITS AVDD VIN Figure 39. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 40. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 41. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ Figure 42. Equivalent SDIO Circuit ...
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... VIN+ and VIN− should be matched, and the inputs should be differentially balanced. Input Common Mode The analog inputs of the AD9613 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V 0 recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin ...
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... ADC. The output common-mode voltage of the ADA4930-2 is easily set with the VCM pin of the AD9613 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 200Ω ...
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... Jitter Considerations section. Figure 52 and Figure 53 show two preferable methods for clocking the AD9613 (at clock rates 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. ...
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... The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9613. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources ...
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... Timing The AD9613 provides latched data with a pipeline delay of 10 input sample clock cycles. Data outputs are available one propagation delay (t PD Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9613 ...
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... AD9613 CHANNEL/CHIP SYNCHRONIZATION The AD9613 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A ...
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... Data Sheet SERIAL PORT INTERFACE (SPI) The AD9613 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9613 part-specific features are described in the Memory Map Register Description section. Table 13. Features Accessible Using the SPI Feature Name Mode ...
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... Address 0x13), this address location should not be written. Default Values After the AD9613 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 14). Logic Levels An explanation of logic level terminology follows: • ...
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... Open (global) 0x0B Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0] (AD9613 = 0x83) (default) Open Open Speed grade 250 MSPS 01 = 210 MSPS 11 = 170 MSPS Open Open Open Open Open Open Open Open ...
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... Open Open 0x00 0x00 … 0x00 … … 0x00 0x00 0x00 0x00 0x00 AD9613 Default Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data Configures the outputs and the format of ...
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... AD9613 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) Pattern 3 LSB (global) 0x1E User Test Pattern 3 MSB (global) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x3A Sync control ...
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... Figure 48. For optimal channel-to-channel isolation Ω resistor should be included between the AD9613 VCM pin and the Channel A analog input network connection, as well as between the AD9613 VCM pin and the Channel B analog input network connection. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required ...
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... Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS Evaluation Board with AD9613, 170 MSPS Evaluation Board with AD9613, 210 MSPS Evaluation Board with AD9613, 250 MSPS D09637-0-9/11(B) Rev ...