AD9613 Analog Devices, AD9613 Datasheet - Page 12

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AD9613

Manufacturer Part Number
AD9613
Description
12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
Manufacturer
Analog Devices
Datasheet

Specifications of AD9613

Resolution (bits)
12bit
# Chan
2
Sample Rate
250MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Bip
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
AD9613
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions for the LFCSP Interleaved Parallel LVDS Mode
Pin No.
ADC Power Supplies
ADC Analog
Digital Input
0
4 to 9, 11, 12, 55, 56, 58
10, 19, 28, 37
49, 50, 53, 54, 59, 60, 63, 64
1
2
51
52
57
61
62
3
Mnemonic
AGND,
Exposed Paddle
DNC
DRVDD
AVDD
CLK+
CLK−
VIN+A
VIN−A
VCM
VIN−B
VIN+B
SYNC
Figure 4. Pin Configuration (Top View) for the LFCSP Interleaved Parallel LVDS Mode
INDICATOR
D0– (LSB)
D0+ (LSB)
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE
DRVDD
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
SYNC
CLK+
CLK–
PIN 1
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
D1–
D1+
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Type
Ground
Supply
Supply
Input
Input
Input
Input
Output
Input
Input
Input
Rev. B | Page 12 of 36
PARALLEL LVDS
(Not to Scale)
TOP VIEW
AD9613
Description
Analog Ground. The exposed thermal paddle on the bottom of the
package provides the analog ground for the part. This exposed paddle
must be connected to ground for proper operation.
Do not connect. Do not connect to these pins.
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
ADC Clock Input—True.
ADC Clock Input—Complement.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Common-Mode Level Bias Output for Analog Inputs. This pin should
be decoupled to ground using a 0.1 μF capacitor.
Differential Analog Input Pin (−) for Channel B.
Differential Analog Input Pin (+) for Channel B.
Digital Synchronization Pin. Slave mode only.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
OR+
OR–
D11+ (MSB)
D11– (MSB)
D10+
D10–
DRVDD
D9+
D9–
D8+
D8–
Data Sheet

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