AD9613 Analog Devices, AD9613 Datasheet - Page 14

no-image

AD9613

Manufacturer Part Number
AD9613
Description
12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
Manufacturer
Analog Devices
Datasheet

Specifications of AD9613

Resolution (bits)
12bit
# Chan
2
Sample Rate
250MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Bip
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
AD9613
Table 9. Pin Function Descriptions for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode
Pin No.
ADC Power Supplies
ADC Analog
Digital Input
Digital Outputs
10, 19, 28, 37
49, 50, 53, 54, 59, 60, 63, 64
4 to 9, 26, 27, 55, 56, 58
0
51
52
62
61
57
1
2
3
7
6
Figure 5. Pin Configuration (Top View) for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode
B D0+/D1+ (LSB)
DNC
AGND, Exposed
Paddle
VIN+A
VIN−A
VIN+B
VIN−B
CLK+
CLK−
SYNC
ORB+
ORB−
B D0–/D1– (LSB)
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE
Mnemonic
DRVDD
AVDD
VCM
ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
INDICATOR
B D2+/D3+
B D4+/D5+
B D2–/D3–
B D4–/D5–
DRVDD
ORB+
SYNC
ORB–
CLK+
CLK–
PIN 1
DNC
DNC
DNC
DNC
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Type
Supply
Supply
Ground
Input
Input
Input
Input
Output
Input
Input
Input
Output
Output
Rev. B | Page 14 of 36
MULTIPLEXED
(Not to Scale)
(EVEN/ODD)
AD9613
CHANNEL
TOP VIEW
LVDS
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Digital Synchronization Pin. Slave mode only.
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect. Do not connect to these pins.
The exposed thermal paddle on the bottom of the package provides
the analog ground for the part. This exposed paddle must be connected
to ground for proper operation.
Common-Mode Level Bias Output for Analog Inputs. This pin should be
decoupled to ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Channel B LVDS Overrange Output—True. The overrange indication is
valid on the rising edge of the DCO.
Channel B LVDS Overrange Output—Complement. The overrange
indication is valid on the rising edge of the DCO.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
ORA+
ORA–
A D10+/D11+ (MSB)
A D10–/D11– (MSB)
A D8+/D9+
A D8–/D9–
DRVDD
A D6+/D7+
A D6–/D7–
A D4+/D5+
A D4–/D5–
Data Sheet

Related parts for AD9613