AD9613 Analog Devices, AD9613 Datasheet - Page 15

• Manufacturer Part Number: AD9613
• Description: 12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9613

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
Pin No.
SPI Control
Output Enable Bar and
Power-Down
11
12
13
14
15
16
17
18
20
21
22
23
29
30
31
32
33
34
35
36
38
39
40
41
43
42
25
24
45
44
46
47
48
Mnemonic
B D0−/D1− (LSB)
B D0+/D1+ (LSB)
B D2−/D3−
B D2+/D3+
B D4−/D5−
B D4+/D5+
B D6−/D7−
B D6+/D7+
B D8−/D9−
B D8+/D9+
B D10−/D11−
B D10+/D11+
A D0−/D1− (LSB)
A D0+/D1+ (LSB)
A D2−/D3−
A D2+/D3+
A D4−/D5−
A D4+/D5+
A D6−/D7−
A D6+/D7+
A D8−/D9−
A D8+/D9+
A D10−/D11−
A D10+/D11+
ORA+
ORA−
DCO+
DCO−
SCLK
SDIO
CSB
OEB
PDWN
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input/Output
Input
Input
Input
Rev. B | Page 15 of 36
Description
Channel B LVDS Output Data 1/Data 0—Complement.
Channel B LVDS Output Data 1/Data 0—True.
Channel B LVDS Output Data 3/Data 2—Complement.
Channel B LVDS Output Data 3/Data 2—True.
Channel B LVDS Output Data 5/Data 4—Complement.
Channel B LVDS Output Data 5/Data 4—True.
Channel B LVDS Output Data 7/Data 6—Complement.
Channel B LVDS Output Data 7/Data 6—True.
Channel B LVDS Output Data 9/Data 8—Complement.
Channel B LVDS Output Data 9/Data 8—True.
Channel B LVDS Output Data 11/Data 10—Complement.
Channel B LVDS Output Data 11/Data 10—True.
Channel A LVDS Output Data 1/Data 0—Complement.
Channel A LVDS Output Data 1/Data 0—True.
Channel A LVDS Output Data 3/Data 2—Complement.
Channel A LVDS Output Data 3/Data 2—True.
Channel A LVDS Output Data 5/Data 4—Complement.
Channel A LVDS Output Data 5/Data 4—True.
Channel A LVDS Output Data 7/Data 6—Complement.
Channel A LVDS Output Data 7/Data 6—True.
Channel A LVDS Output Data 9/Data 8—Complement.
Channel A LVDS Output Data 9/Data 8—True.
Channel A LVDS Output Data 11/Data 10—Complement.
Channel A LVDS Output Data 11/Data 10—True.
Channel A LVDS Overrange Output—True. The overrange indication is
valid on the rising edge of the DCO.
Channel A LVDS Overrange Output—Complement. The overrange
indication is valid on the rising edge of the DCO.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
Output Enable Bar Input (Active Low).
Power-Down Input (Active High). Operation depends upon SPI mode;
this input can be configured as power-down or standby. For further
description, refer to Table 14.
AD9613