AD9613 Analog Devices, AD9613 Datasheet - Page 2

• Manufacturer Part Number: AD9613
• Description: 12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9613

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9613
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings.......................................................... 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 16
Equivalent Circuits ......................................................................... 22
Theory of Operation ...................................................................... 23
REVISION HISTORY
9/11—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
Changes to Temperature Drift Parameters ................................... 3
Changes Output Offset Voltage (V
Parameter and Output Offset Voltage (V
Mode Parameter................................................................................ 7
Changes to Output Enable Bar and Power-Down Pin Type
and Pin 47 Description .................................................................. 13
Changes to Figure 5 and Pin 7 and Pin 8 Descriptions ............. 14
Changes to Pin 42 and Pin 43, Output Enable Bar and Power-
Down Pin Type, and Pin 47 Descriptions ................................... 15
Changes to Typical Performance Characteristics Conditions .. 16
Changes to Fiugre 43...................................................................... 22
Added ADC Overrange (OR) Section ......................................... 27
ADC DC Specifications ............................................................... 3
ADC AC Specifications ............................................................... 4
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Thermal Characteristics ............................................................ 11
ESD Caution................................................................................ 11
ADC Architecture ...................................................................... 23
OS
), ANSI Mode Typ
OS
), Reduced Swing
Rev. B | Page 2 of 36
Channel/Chip Synchronization.................................................... 28
Serial Port Interface (SPI).............................................................. 29
Memory Map .................................................................................. 31
Applications Information .............................................................. 35
Outline Dimensions ....................................................................... 36
Changes to Channel/Chip Synchronization Section ................. 28
Changes to Reading the Memory Map Register Table
Section and Transfer Register Map Section ................................ 31
Changes to Register 0x02, Bits[5:4] ............................................. 32
Changes to Register 0x16, Bit 5 .................................................... 33
Added Register 0x3A ..................................................................... 34
Deleted Register 0x59 .................................................................... 34
Changes to Bit 0—Master Sync Buffer Enable Section ............. 34
Deleted SYNC Pin Control (Register 0x59) Section.................. 34
5/11—Rev. 0 to Rev. A
Changes to Table 2, AD9613-170: Worst Second or Third
Harmonic and Worst Other (Harmonic or Spur) Max Values
and Spurious Free Dynamic Range Min Value .............................4
4/11—Revision 0: Initial Version
Analog Input Considerations ................................................... 23
Voltage Reference ....................................................................... 25
Clock Input Considerations...................................................... 25
Power Dissipation and Standby Mode .................................... 27
Digital Outputs ........................................................................... 27
ADC Overrange (OR)................................................................ 27
Configuration Using the SPI..................................................... 29
Hardware Interface..................................................................... 29
SPI Accessible Features.............................................................. 30
Reading the Memory Map Register Table............................... 31
Memory Map Register Table..................................................... 32
Memory Map Register Description ......................................... 34
Design Guidelines ...................................................................... 35
Ordering Guide .......................................................................... 36
Data Sheet