AD9613 Analog Devices, AD9613 Datasheet - Page 25

• Manufacturer Part Number: AD9613
• Description: 12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9613

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9613.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9613 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal. The
signal is typically ac-coupled into the CLK+ and CLK− pins via
a transformer or via capacitors. These pins are biased internally
(see Figure 51) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
Clock Input Options
The AD9613 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 52 and Figure 53 show two preferable methods for clocking
the AD9613 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9613 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
CLK+
Figure 51. Simplified Equivalent Clock Input Circuit
Figure 50. Differential Input Configuration Using the AD8376 (Filter Values Shown for a 20 MHz Bandwidth Filter Centered at 140 MHz)
4pF
AVDD
0.9V
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
2. FILTER VALUES SHOWN FOR A 20MHz BANDWIDTH FILTER
AD8376
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
CENTERED AT 140MHz.
1µH
1µH
4pF
1000pF
1000pF
VPOS
CLK–
1nF
180nH
301Ω
180nH
Rev. B | Page 25 of 36
5.1pF
220nH
220nH
3.9pF
165Ω
165Ω
the clock from feeding through to other portions of the AD9613,
while preserving the fast rise and fall times of the signal, which are
critical to low jitter performance.
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 54. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,
AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/
ADCLK925
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
VCM
15pF
1nF
CLOCK
INPUT
Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)
50kΩ
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
68nH
50Ω
390pF
clock drivers offer excellent jitter performance.
390pF
2.5kΩ║2pF
0.1µF
0.1µF
50kΩ
AD9613
100Ω
ADT1-1WT, 1:1Z
Mini-Circuits
AD95xx
PECL DRIVER
XFMR
25Ω
25Ω
240Ω
390pF
390pF
390pF
390pF
®
DIODES: HSMS2822
SCHOTTKY
HSMS2822
DIODES:
SCHOTTKY
240Ω
0.1µF
0.1µF
CLK+
CLK–
100Ω
CLK+
CLK–
ADC
AD9613
CLK+
CLK–
ADC
ADC