AD9613 Analog Devices, AD9613 Datasheet - Page 34

• Manufacturer Part Number: AD9613
• Description: 12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9613

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9613
Addr
(Hex)
0x1E
0x1F
0x20
0x24
0x25
0x3A
1
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x25, see the
to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync buffer enable bit (Address 0x3A, Bit 0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse that
The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00.
Register
Name
Pattern 3 LSB
(global)
User Test
Pattern 3 MSB
(global)
User Test
Pattern 4 LSB
(global)
User Test
Pattern 4 MSB
(global)
BIST signature
LSB (local)
BIST signature
MSB (local)
Sync control
(global)
Bit 7
(MSB)
Open
AN-877
Application Note, Interfacing
Bit 6
Open
Bit 5
Open
Bit 4
Open
User Test Pattern 3[15:8]
User Test Pattern 4[15:8]
User Test Pattern 4[7:0]
Rev. B | Page 34 of 36
BIST signature[15:8]
BIST signature[7:0]
Bit 3
Open
it receives and to ignore the rest. The clock divider sync enable
bit (Address 0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Buffer Enable
Bit 0 must be set high to enable any of the sync functions. If
the sync capability is not used, this bit should remain low to
conserve power.
Bit 2
Clock
divider
next sync
only
Bit 1
Clock
divider
sync
enable
Bit 0
(LSB)
Master sync
buffer enable
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
Data Sheet
Read only
Default
Notes/
Comments
Read only