AD9613 Analog Devices, AD9613 Datasheet - Page 6

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AD9613

Manufacturer Part Number
AD9613
Description
12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
Manufacturer
Analog Devices
Datasheet

Specifications of AD9613

Resolution (bits)
12bit
# Chan
2
Sample Rate
250MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Bip
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
AD9613
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
SYNC INPUT
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK)
LOGIC INPUTS (SDIO)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
1
2
1
Rev. B | Page 6 of 36
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
0.3
AGND
0.9
10
−22
8
AGND
1.2
AGND
−5
−5
12
1.22
0
−5
−80
1.22
0
45
−5
1.22
0
45
−5
CMOS/LVDS/LVPECL
CMOS/LVDS
Typ
4
10
0.9
1
16
26
2
26
2
26
5
0.9
Max
3.6
AVDD
1.4
22
−10
12
AVDD
AVDD
0.6
+5
+5
20
2.1
0.6
+5
+45
2.1
0.6
70
+5
2.1
0.6
70
+5
Data Sheet
Unit
V
V p-p
V
V
μA
μA
pF
V
V
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF

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