AD9643

Manufacturer Part NumberAD9643
Description14-Bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
ManufacturerAnalog Devices
AD9643 datasheet
 


Specifications of AD9643

Resolution (bits)14bit# Chan2
Sample Rate250MSPSInterfaceLVDS,Par
Analog Input TypeDiff-BipAin Range1.75 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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Data Sheet
FEATURES
SNR = 70.6 dBFS at 185 MHz A
and 250 MSPS
IN
SFDR = 85 dBc at 185 MHz A
and 250 MSPS
IN
−151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A
250 MSPS
Total power consumption: 785 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The AD9643 is a dual, 14-bit analog-to-digital converter (ADC)
with sampling speeds of up to 250 MSPS. The AD9643 is designed
to support communications applications, where low cost, small
size, wide bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC output data is routed directly to the two external
14-bit LVDS output ports and formatted as either interleaved or
channel multiplexed.
Flexible power-down options allow significant power savings,
when desired.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V
Dual Analog-to-Digital Converter ( ADC)
and
VIN+A
IN
VIN–A
VCM
VIN+B
VIN–B
NOTES
1. THE D0± TO D13± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNE L B LVDS OUTPUT DATA.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The AD9643 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.
2. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating LVDS outputs.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
4. SYNC input allows synchronization of multiple devices.
5. 3-pin, 1.8 V SPI port for register programming and register
readback.
6. Pin compatibility with the AD9613, allowing a simple
migration down from 14 bits to 12 bits. This part is also pin
compatible with the
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9643
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
PIPELINE
14-BIT
14
ADC
AD9643
PARALLEL
DDR LVDS
PIPELINE
AND
14-BIT
14
DRIVERS
ADC
REFERENCE
1 TO 8
SERIAL PORT
CLOCK
DIVIDER
SCLK
SDIO
CSB
CLK+
CLK–
SYNC
Figure 1.
AD6649
and the AD6643.
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
D0±
.
.
.
.
.
D13±
DCO±
OR±
OEB
PDWN

AD9643 Summary of contents

  • Page 1

    ... Broadband data applications GENERAL DESCRIPTION The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) with sampling speeds 250 MSPS. The AD9643 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic ...

  • Page 2

    ... AD9643 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 ADC DC Specifications ............................................................... 3 ADC AC Specifications ............................................................... 4 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 11 Thermal Characteristics ............................................................ 11 ESD Caution................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 Typical Performance Characteristics ........................................... 16 Equivalent Circuits ......................................................................... 22 Theory of Operation ...

  • Page 3

    ... Rev Page AD9643 AD9643-250 Max Min Typ Max Unit 14 Bits Guaranteed ±10 ±10 mV +3/−5 ±4 %FSR ±0.75 ±0.75 LSB ±0.25 LSB ±2 ±3.5 LSB ±1.5 LSB ±13 ±13 mV − ...

  • Page 4

    ... Rev Page Data Sheet AD9643-250 Max Min Typ Max Unit 72.0 dBFS 71.7 dBFS dBFS 71.4 dBFS 70.9 dBFS 68.8 dBFS 70.5 dBFS 71.0 dBFS 70.7 dBFS dBFS 70.4 dBFS 69.9 dBFS 67 ...

  • Page 5

    ... Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally. AD9643-170 AD9643-210 Min Typ Max Min Typ 95 95 400 400 1000 1000 Rev Page AD9643 AD9643-250 Max Min Typ Max Unit 95 dB 400 MHz 1000 MHz ...

  • Page 6

    ... AD9643 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range ...

  • Page 7

    ... Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode 1 Pull-up. 2 Pull-down. Temp Min Full 250 Full 1.15 Full 150 Full 1.15 Rev Page AD9643 Typ Max Unit 350 450 mV 1.22 1.35 V 200 280 mV 1.22 1.35 V ...

  • Page 8

    ... Full 5.8 4.8 Full 2.61 2.9 3.19 2.16 Full 2.76 2.9 3.05 2.28 Full 0.8 0.8 Full 1.0 Full 0.1 Full 4.8 Full 5.5 Full 0.3 0.7 1.1 0.3 Full 10 Full 1.0 Full 0.1 Full 10 Full 250 Full 3 Rev Page Data Sheet AD9643-210 AD9643-250 Typ Max Min Typ 625 210 40 4 2.4 2.64 1.8 2.0 2.4 2.52 1.9 2.0 0.8 1.0 1.0 0.1 0.1 4.8 4.8 5.5 5.5 0.7 1.1 0.3 0 1.0 1.0 0.1 0 250 250 3 3 Max Unit 625 MHz 250 ...

  • Page 9

    ... Time required for the SDIO pin to switch from an input to an output EN_SDIO relative to the SCLK falling edge t Time required for the SDIO pin to switch from an output to an input DIS_SDIO relative to the SCLK rising edge Rev Page AD9643 Min Typ Max Unit 0.3 ns 0.4 ...

  • Page 10

    ... AD9643 Timing Diagrams VIN CLK+ CLK– DCO– DCO+ PARALLEL INTERLEAVED D0± (LSB CHANNEL A AND . CHANNEL B D13± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE (LSB CHANNEL A . D12±/D13± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE (LSB CHANNEL B . D12± ...

  • Page 11

    ... ESD CAUTION Rev Page Airflow Velocity (m/sec) θ θ 26.8 1.14 1.0 21.6 2.0 20.2 is specified for a 4-layer PCB with a solid ground addition, metal in direct contact with the AD9643 1, 4 θ Unit JB 10.4 °C/W °C/W °C/W ...

  • Page 12

    ... D2+ 13 D2− 16 D3+ 15 D3− 18 D4+ PIN 1 CLK+ 1 CLK– 2 SYNC 3 DNC 4 DNC 5 DNC 6 AD9643 DNC 7 8 PARALLEL LVDS 9 TOP VIEW (Not to Scale) DRVDD 10 D1– 11 D1+ 12 D2– 13 D2+ 14 D3– 15 D3+ 16 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. ...

  • Page 13

    ... Input/Output SPI Serial Data I/O. Input SPI Chip Select (Active Low). Input/Output Output Enable Bar Input (Active Low). Input/Output Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14). Rev Page AD9643 ...

  • Page 14

    ... DNC 57 VCM 1 CLK+ 2 CLK− Digital Input 3 SYNC PIN 1 CLK+ 1 CLK– 2 SYNC 3 DNC 4 DNC 5 AD9643 DNC 6 CHANNEL DNC 7 MULTIPLEXED 8 (EVEN/ODD) 9 LVDS 10 TOP VIEW 11 (Not to Scale NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART ...

  • Page 15

    ... SPI Serial Data Input/Output. Input SPI Chip Select (Active Low). Input Output Enable Bar Input (Active Low). Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power- down or standby (see Table 14). Rev Page AD9643 ...

  • Page 16

    ... Figure 8. AD9643-170 Single-Tone FFT with f THIRD HARMONIC 90.1 MHz Figure 9. AD9643-170 Single-Tone SNR/SFDR vs. Input Amplitude ( Figure 10. AD9643-170 Single-Tone SNR/SFDR vs. Input Frequency (f = 185.1 MHz IN SECOND HARMONIC 305.1 MHz Figure 11. AD9643-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN Rev Page 120 ...

  • Page 17

    ... IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –78.5 –67.0 –55.5 –44.0 INPUT AMPLITUDE (dBFS) Figure 12. AD9643-170 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 184.12 187.12 MHz, f IN1 IN2 0 170MSPS 89.12MHz @ –7dBFS –20 92.12MHz @ –7dBFS SFDR = 89dBc (96dBFS) –40 –60 – ...

  • Page 18

    ... MHz Figure 21. AD9643-210 Single-Tone SNR/SFDR vs. Input Frequency (f IN –20 –40 –60 –80 –100 –120 100 = 305.1 MHz Figure 22. AD9643-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN –20 –40 –60 –80 –100 –120 –30 –20 – Figure 23. AD9643-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN Rev ...

  • Page 19

    ... Figure 25. AD9643-210 Two-Tone FFT with f IN1 f = 210 MSPS S 100 100 120 140 SAMPLE RATE (MSPS) Figure 26. AD9643-210 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 90.1 MHz 100 = 89.12 92.12 MHz, IN2 100 = 184.12 187.12 MHz, IN2 SNR, CHANNEL B SFDR, CHANNEL B ...

  • Page 20

    ... Figure 32. AD9643-250 Single-Tone SNR/SFDR vs. Input Frequency (f SECOND HARMONIC 80 90 100 110 120 = 305.1 MHz Figure 33. AD9643-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN –30 –20 – Figure 34. AD9643-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN 200 220 240 260 Figure 35. AD9643-250 Two-Tone FFT with Rev Page –20 SFDR (dBc) – ...

  • Page 21

    ... MSPS S 100 100 120 140 160 SAMPLE RATE (MSPS) Figure 37. AD9643-250 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 90.1 MHz 100 110 120 = 184.12 187.12 MHz, IN2 SNR, CHANNEL B SFDR, CHANNEL B SNR, CHANNEL A SFDR, CHANNEL A 180 200 220 240 ...

  • Page 22

    ... AD9643 EQUIVALENT CIRCUITS AVDD VIN Figure 39. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 40. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 41. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ Figure 42. Equivalent SDIO Circuit SCLK, PDWN, Figure 43 ...

  • Page 23

    ... VIN+ and VIN− should be matched, and the inputs should be differentially balanced. Input Common Mode The analog inputs of the AD9643 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V 0 recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin ...

  • Page 24

    ... AD9643 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the set with the VCM pin of the AD9643 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to provide band-limiting of the input signal. 200Ω ...

  • Page 25

    ... Jitter Considerations section. Figure 52 and Figure 53 show two preferable methods for clocking the AD9643 (at clock rates 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. ...

  • Page 26

    ... Sampled Systems and the Effects of Clock Phase Noise and Jitter, for more information about jitter performance as it relates to ADCs. POWER DISSIPATION AND STANDBY MODE As shown in Figure 57, the power dissipated by the AD9643 is proportional to its sample rate. The data in Figure 57 was taken using the same operating conditions as those used for the Typical Performance Characteristics section. − ...

  • Page 27

    ... The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9643. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9643 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance may degrade. Data Clock Output (DCO) The AD9643 also provides data clock output (DCO) intended for capturing the data in an external register ...

  • Page 28

    ... AD9643 CHANNEL/CHIP SYNCHRONIZATION The AD9643 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The SYNC feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A ...

  • Page 29

    ... ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9643 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. Rev Page ...

  • Page 30

    ... SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9643 part-specific features are described in the Memory Map Register Description section. Table 13. Features Accessible Using the SPI Feature Name Description ...

  • Page 31

    ... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9643 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 14. Logic Levels An explanation of logic level terminology follows: • ...

  • Page 32

    ... Open (global) 0x0B Open Open Clock divide (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0] (AD9643 = 0x82) (default) Speed grade ID Open Open 00 = 250 MSPS 01 = 210 MSPS 11 = 170 MSPS Open Open Open Open Open Open Open Open External ...

  • Page 33

    ... V p-p … 00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p User Test Pattern 1[7:0] User Test Pattern 1[15:8] User Test Pattern 2[7:0] User Test Pattern 2[15:8] Rev Page AD9643 Default Default Bit 0 Value Notes/ Bit 1 (Hex) Comments (LSB) 0x00 When this register is ...

  • Page 34

    ... AD9643 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) 0x1D User Test Pattern 3 LSB (global) 0x1E User Test Pattern 3 MSB (global) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) ...

  • Page 35

    ... Figure 48. For optimal channel-to-channel isolation Ω resistor should be included between the AD9643 VCM pin and the Channel A analog input network connection, as well as between the AD9643 VCM pin and the Channel B analog input network connection. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required ...

  • Page 36

    ... Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board with AD9643-170 Evaluation Board with AD9643-210 Evaluation Board with AD9643-250 D09636-0-9/11(B) Rev ...