AD9643 Analog Devices, AD9643 Datasheet - Page 27

• Manufacturer Part Number: AD9643
• Description: 14-Bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9643

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
DIGITAL OUTPUTS
The AD9643 output drivers can be configured for either ANSI
LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.
As detailed in the
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD9643 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OEB pin
or through the SPI interface. If the OEB pin is low, the output
data drivers are enabled. If the OEB pin is high, the output data
drivers are placed in a high impedance state. This OEB function
is not intended for rapid access to the data bus. Note that OEB
is referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI interface, the data outputs of each channel
can be independently three-stated by using the output enable
bar bit (Bit 4) in Register 0x14. Because the output data is
interleaved, if only one of the two channels is disabled, the output
data of the remaining channel is repeated in both the rising and
falling output clock cycles.
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
AN-877 Application
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
<–0.875
–0.875
0
+0.875
>+0.875
Note, Interfacing to High
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. B | Page 27 of 36
Timing
The AD9643 provides latched data with a pipeline delay of 10 input
sample clock cycles. Data outputs are available one propagation
delay (t
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9643.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9643 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD9643 also provides data clock output (DCO) intended
for capturing the data in an external register. Figure 2 shows a
graphical timing diagram of the AD9643 output modes.
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clocks. An overrange at the input is
indicated by this bit, 10 clock cycles after it occurs.
PD
) after the rising edge of the clock signal.
Twos Complement Mode (Default)
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
AD9643
OR
1
0
0
0
1