AD9641 Analog Devices, AD9641 Datasheet - Page 19

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9641.
The input full-scale range can be adjusted through the SPI port by
adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be
used to change the full-scale value between 1.383 V p-p and
2.087 V p-p in 0.022 V steps, as shown in Table 17.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
by means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 53) and require no
external bias. If the inputs are floated, the CLK− pin is pulled low
to prevent spurious clocking.
Clock Input Options
The
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section. The
minimum conversion rate of the
rates below 40 MSPS, dynamic performance of the
degrade.
Figure 54 and Figure 55 show two preferred methods for clocking
the
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
CLOCK
CLOCK
INPUT
INPUT
AD9641
AD9641
Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)
CLK+
50Ω
0.1µF
(at clock rates up to 640 MHz). A low jitter clock
has a very flexible clock input structure. Clock input
50Ω
1nF
Figure 53. Equivalent Clock Input Circuit
1nF
4pF
100Ω
ADT1-1WT, 1:1Z
Mini-Circuits
XFMR
0.1µF
AVDD
0.9V
®
0.1µF
0.1µF
0.1µF
0.1µF
AD9641
AD9641
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
is 40 MSPS. At clock
sample clock inputs,
4pF
CLK+
CLK–
AD9641
CLK+
CLK–
CLK–
ADC
ADC
can
Rev. B | Page 19 of 36
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 640 MHz, and the RF transformer is
recommended for clock frequencies from 40 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the
mately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 56. The
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/
AD9520/AD9522
CLOCK
CLOCK
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 57. The
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518/AD9520/AD9522
performance.
CLOCK
CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor (see Figure 58).
CLOCK
*50Ω RESISTOR IS OPTIONAL.
INPUT
INPUT
INPUT
INPUT
INPUT
Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)
Figure 56. Differential PECL Sample Clock (Up to 640 MHz)
50Ω*
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ
50kΩ
V
CC
clock drivers offer excellent jitter performance.
1kΩ
1kΩ
AD95xx
PECL DRIVER
AD95xx
LVDS DRIVER
AD95xx
CMOS DRIVER
clock drivers offer excellent jitter
240Ω
AD9510/AD9511/AD9512/
OPTIONAL
240Ω
100Ω
0.1µF
0.1µF
0.1µF
AD9641
100Ω
0.1µF
0.1µF
0.1µF
100Ω
AD9641
to approxi-
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
AD9641
AD9510/
ADC
ADC
ADC
while