AD9641 Analog Devices, AD9641 Datasheet - Page 22

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
Figure 61 shows a simplified block diagram of the JESD204A link
for the AD9641. The 8b/10b encoding works by taking eight bits of
data (an octet) and encoding them into a 10-bit symbol. By default
in the AD9641, the 14-bit converter word is broken into two octets.
Bit 13 through Bit 6 are in the first octet. The second octet contains
Bit 5 through Bit 0 and two tail bits. The MSB of the tail bits can
also be used to indicate an out-of-range condition. The tail bits
are configured using the JESD204A link control in JESD204A
Link Control Register 1, Address 0x60, Bit 6.
CONVERTER
INPUT
Figure 61.
CONVERTER
AD9641
TIME
Transmit Link Simplified Block Diagram
TRANSMITTER
CONVERTER
SAMPLE
AD9641 ADC
FROM
DATA
ADC
FROM
WORD 0[5:0], TAIL BITS[1:0]
WORD 1[5:0], TAIL BITS[1:0]
(M = 0, 1; L = 0, 1)
JESD204 A LINK
WORD 0[13:6]
WORD 1[13:6]
DECODER
(ADD TAIL BITS)
8B/10B
ASSEMBLER
Figure 63. 14-Bit Data Transmission with Tail Bits
FRAME
Figure 64. Required Receiver Data Path
LINK
DSYNC
OUTPUT
LANE
Figure 62. ADC Output Data Path
Rev. B | Page 22 of 36
DESCRAMBLER
1 + x
OPTIONAL
SCRAMBLER
1 + x
14
OPTIONAL
+ x
14
15
+ x
15
The two resulting octets are optionally scrambled and encoded
into their corresponding 10-bit code. The scrambler function is
controlled by the JESD204A scrambling and lane configuration
register, Address 0x06E, Bit 7. Figure 62 shows how the 14-bit
data is taken from the ADC, the tail bits are added, the two octets
are scrambled, and the octets are encoded into two 10-bit symbols.
Figure 63 illustrates the default data format.
The scrambler uses a self-synchronizing, polynomial-based
algorithm defined by the following equation: 1 + x
descrambler in the receiver should be a self-synchronizing
version of the scrambler polynomial. Figure 64 shows the
corresponding receiver data path.
Refer to JEDEC Standard No. 204A, April 2008, Section 5.1, for
complete transport layer and data format details. See Section 5.2
for a complete explanation of scrambling and descrambling.
SYMBOL 0[9:0]
SYMBOL 1[9:0]
SYMBOL 2[9:0]
SYMBOL 3[9:0]
ALIGNMENT
FRAME
ENCODER
8B/10B
TO
RECEIVER
DATA
OUT
FRAME 0
FRAME 1
Data Sheet
14
+ x
15
. The