AD9641 Analog Devices, AD9641 Datasheet - Page 23

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
Initial Frame Synchronization
The serial interface must synchronize to the frame boundaries
before data can be properly decoded. The JESD204A standard
has a synchronization routine to identify the frame boundary.
When the DSYNC pin is taken low for at least two clock cycles,
the
AD9641
achieves synchronization. The receiver should then deassert the
sync signal (take DSYNC high), and the
lane alignment sequence (when enabled through Address 0x60,
Bits[3:2]) and, subsequently, begins transmitting sample data. The
first non-K28.5 symbol corresponds to the first octet in a frame.
The DSYNC input can be driven either from a differential LVDS
source or by using a single-ended CMOS driver circuit. The
DSYNC input default to LVDS mode but can be set to CMOS
mode by setting Bit 4 in Address 0x61. If it is driven differen-
tially from an LVDS source, an external 100 Ω termination
resistor should be provided. If the DSYNC input is driven single
endedly, the CMOS signal should be connected to the DSYNC+
signal, and the DSYNC− signal should be left disconnected.
Frame and Lane Alignment Monitoring and Correction
Frame alignment monitoring and correction is part of the
JESD204A specification. The 14-bit word requires two octets to
transmit all the data. The two octets (MSB and LSB), where
F = 2, make up a frame. During normal operating conditions,
frame alignment is monitored via alignment characters, which
are inserted under certain conditions at the end of a frame.
Table 11 summarizes the conditions for character insertion,
along with the expected characters under the various operation
modes. If lane synchronization is enabled, the replacement
character value depends on whether the octet is at the end of
a frame or at the end of a multiframe.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replace characters.
Digital Outputs and Timing
The
by default. The driver current is derived on-chip and sets the
output current at each output equal to a nominal 4 mA. Each
output presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
Table 11.
Scrambling
Off
Off
Off
On
On
On
AD9641
AD9641
transmits the K28.5 comma symbol until the receiver
AD9641
enters the code group synchronization mode. The
has differential digital outputs that power up
Lane
Synchronization
On
On
Off
On
On
Off
JESD204A Frame Alignment Monitoring and Correction Replacement Characters
Character to Be Replaced
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7 (0xFC)
Last octet in frame equals D28.3 (0x7C)
Last octet in frame equals D28.7 (0x7C)
AD9641
begins the initial
Rev. B | Page 23 of 36
A 100 Ω differential termination resistor should be placed at each
receiver input to result in a nominal 400 mV peak-to-peak swing at
the receiver (see Figure 65). Alternatively, single-ended 50 Ω
termination can be used. When single-ended termination is
used, the termination voltage should be DRVDD/2; otherwise,
ac coupling capacitors can be used to terminate to any single-
ended voltage.
The
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close as possible to the receiver logic. The common
mode of the digital output automatically biases itself to half the
supply of the receiver (that is, the common-mode voltage is 0.9 V
for a receiver supply of 1.8 V) if dc-coupled connecting is used
(see Figure 66).
For receiver logic that is not within the bounds of the DRVDD
supply, an ac-coupled connection should be used. Place a 0.1 μF
capacitor on each output pin and derive a 100 Ω differential
termination close to the receiver side.
If there is no far-end receiver termination or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than 8 inches and that the differential output traces be close
together and at equal lengths.
OUTPUT SWING = 400mV p-p
OUTPUT SWING = 400mV p-p
AD9641
DOUT+x
DOUT–x
DRVDD
DOUT + x
DOUT – x
Figure 66. DC-Coupled Digital Output Termination Example
Figure 65. AC-Coupled Digital Output Termination Example
DRVDD
digital outputs can interface with custom ASICs and
0.1µF
0.1µF
Last Octet in Multiframe
No
Yes
Not applicable
No
Yes
Not applicable
DIFFERENTIAL
DIFFERENTIAL
TRACE PAIR
TRACE PAIR
100Ω
100Ω
100Ω
100Ω
V
OR
RXCM
RECEIVER
V
V
CM
CM
RECEIVER
= DRVDD/2
= Rx V
Replacement
Character
K28.7 (0xFC)
K28.3 (0x7C)
K28.7 (0xFC)
K28.7 (0xFC)
K28.3 (0x7C)
K28.7 (0xFC)
AD9641
CM