AD9641 Analog Devices, AD9641 Datasheet - Page 30

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
Addr
(Hex)
ADC Functions
0x08
0x09
0x0A
0x0B
0x0D
0x0E
0x10
0x14
0x15
0x18
0x19
0x1A
0x1B
0x1C
0x1D
Register
Name
Power
modes
Global clock
PLL status
Clock divide
Test mode
BIST enable
Offset adjust
Output
mode
Output
adjust
Input span
select
User Test
Pattern 1 LSB
User Test
Pattern 1 MSB
User Test
Pattern 2 LSB
User Test
Pattern 2 MSB
User Test
Pattern 3 LSB
Bit 7
(MSB)
Open
Open
PLL locked
Open
User test
mode
control
0 =
continuous/
repeat
pattern
1 = single
pattern
Open
Open
Open
Open
Open
Bit 6
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Bit 5
External
power-
down pin
function
0 = PDWN
1 = STNDBY
Open
Open
Reset PN
long gen
Open
Open
Open
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
User Test Pattern 1, Bits[15:8]
User Test Pattern 2, Bits[15:8]
User Test Pattern 1, Bits[7:0]
User Test Pattern 2, Bits[7:0]
User Test Pattern 3, Bits[7:0]
Bit 4
Open
Open
Open
Reset PN
short gen
Open
Output
disable
Open
Rev. B | Page 30 of 36
Offset adjust in LSBs from +31 to −32
Bit 3
Open
Open
Open
Open
Open
Open
(twos complement format)
Full scale input voltage selection
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one-/zero- word toggle
1000 = user test mode
1001 to 1110 = unused
1111 = ramp output
00000 = 1.75 V p-p (default)
01111 = 2.087 V p-p
00001 = 1.772 V p-p
11111 = 1.727 V p-p
10000 = 1.383 V p-p
Bit 2
Open
Open
Open
Reset BIST
sequence
Output
invert
Open
…
…
Clock divide ratio
000 = divide-by-1
001 = divide-by-2
010 = divide-by-3
011 = divide-by-4
100 = divide-by-5
101 = divide-by-6
110 = divide-by-7
111 = divide-by-8
Bit 1
Internal power-down mode
Open
Open
Open
Output drive level adjust
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
Output format
00 = offset binary
01 = twos complement
(default)
01 = Gray code
11 = offset binary
11 = 320 mV
00 = 400 mV
10 = 440 mV
01 = 500 mV
Bit 0
(LSB)
Duty cycle
stabilizer
(default)
Open
BIST enable
Default
Value
(Hex)
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Data Sheet
Default
Notes/
Comments
Determines
various
generic
modes of
chip
operation.
Read only.
Clock divide
values other
than 000
cause the
duty cycle
stabilizer to
become
active.
When this
register is
set, the
test data is
placed on
the output
pins in place
of normal
data.
Configures
the outputs
and the
format of
the data.
Full-scale
input
adjustment
in 0.022 V
steps.