AD9641 Analog Devices, AD9641 Datasheet - Page 32

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
Addr
(Hex)
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0x25, see the
Interfacing to High Speed ADCs via SPI.
Sync Control (Address 0x3A)
Bits[7:3]—Open
Bit 2—Clock Divider Next Sync Only
If the master sync buffer enable bit (Address 0x3A, Bit 0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
Register
Name
JESD204A
number of
octets per
frame (F)
JESD204A
number of
frames per
multiframe
(K)
JESD204A
number of
converters
per link per
converter
device (link)
(M)
JESD 204A
converter
resolution (N)
and control
bits per
sample (CS)
JESD204A
total bits per
sample (N’)
JESD204A
samples per
converter (S)
per frame
cycle
JESD204A
HD and CF
configuration
JESD204A
Serial
Reserved
Field 1
(RES1)
JESD204A
Serial
Reserved
Field 2
(RES2)
JESD204A
checksum
value for
lane (FCHK)
Bit 7
(MSB)
Open
Open
Open
Open
Enable HD
(high
density)
format
Number of control bits per
10 = two control bits
00 = no control bits
01 = one control bit
11 = unused
sample (CS)
(CS = 0)
(CS = 1)
(CS = 2)
Bit 6
Open
Open
Open
Open
Open
AN-877
Application Note,
(bits are calculated based on the equation F = (M × 2)/L)
Bit 5
Open
Open
Open
Open
Open
Open
(these registers are available for customer use)
(these registers are available for customer use)
JESD204A number of octets per frame (F)
Serial checksum value for lane (FCHK)
Serial Reserved Field 1 (RES1)
Serial Reserved Field 2 (RES2)
Bit 4
Rev. B | Page 32 of 36
Open
Number of control words per frame clock cycle per link (CF)
Samples per converter per frame cycle (S) (read only)
Total number of bits per sample (N’) (read only)
JESD204A number of frames per multiframe (K)
Bit 3
(always 0 for the
Converter resolution (N) (read only)
Open
receives and to ignore the rest. The clock divider sync enable bit
(Address 0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is enabled when Bit 1 and Bit 0 are high. This is in continuous
sync mode.
Bit 0—Master Sync Buffer Enable
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used, this bit should remain low to
conserve power.
(always 1 for the AD9641)
Bit 2
Open
AD9641
(read only))
Bit 1
Open
Bit 0
(LSB)
Number of
converters
per link
per device
0 = link
connected to
one ADC
(M = 1)
1 = reserved
Default
Value
(Hex)
0x01
0x0F
0x00
0x4D
0x0F
0x00
0x00
0x00
0x00
0x00
Data Sheet
Default
Notes/
Comments
Read only.
Read only.
Read only.
Read only.
Read only