AD7607 Analog Devices, AD7607 Datasheet - Page 6

• Manufacturer Part Number: AD7607
• Description: 8-Channel DAS with 14-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7607

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: SE-Bip
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7607
TIMING SPECIFICATIONS
AV
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
PARALLEL/BYTE READ
t
t
OPERATION
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CC
OS_SETUP
OS_HOLD
CYCLE
CONV
WAKE-UP STANDBY
WAKE-UP SHUTDOWN
RESET
1
2
3
4
5
6
7
8
9
10
11
12
2
Internal Reference
External Reference
= 4.75 V to 5.25 V, V
DRIVE
= 2.3 V to 5.25 V, V
Min
3.45
7.87
16.05
33
66
133
257
50
20
20
25
25
0
25
0
0
16
21
25
32
15
22
Limit at T
Typ
5
4
MIN
REF
, T
MAX
= 2.5 V external reference/internal reference, T
Max
5
9.1
4.15
9.1
18.8
39
78
158
315
100
30
13
40
0.5
25
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 6 of 32
Description
1/throughput rate
Parallel mode, reading during or after conversion; or serial mode (V
3.3 V to 5.25 V), reading during a conversion using D
Serial mode reading during conversion; V
Serial mode reading after a conversion; V
Conversion time
Oversampling off
Oversampling by 2
Oversampling by 4
Oversampling by 8
Oversampling by 16
Oversampling by 32
Oversampling by 64
STBY rising edge to CONVST x rising edge; power-up time from
standby mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CS rising edge and BUSY falling edge
Minimum delay between RESET low to CONVST x high
CS to RD setup time
CS to RD hold time
RD low pulse width
V
V
V
V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
DRIVE
DRIVE
DRIVE
DRIVE
above 4.75 V
above 3.3 V
above 2.7 V
above 2.3 V
A
= T
MIN
to T
DRIVE
DRIVE
MAX
= 2.3 V, D
= 2.7 V
, unless otherwise noted.
OUT
OUT
Data Sheet
A and D
A and D
OUT
OUT
B lines
B lines
DRIVE
1
=