AD7607 Analog Devices, AD7607 Datasheet - Page 8

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AD7607

Manufacturer Part Number
AD7607
Description
8-Channel DAS with 14-Bit, Bipolar, Simultaneous Sampling ADC
Manufacturer
Analog Devices
Datasheet

Specifications of AD7607

Resolution (bits)
14bit
# Chan
8
Sample Rate
200kSPS
Interface
Par,Ser,SPI
Analog Input Type
SE-Bip
Ain Range
Bip 10V,Bip 5.0V
Adc Architecture
SAR
Pkg Type
QFP

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AD7607
Parameter
1
2
3
Timing Diagrams
Sample tested during initial release to ensure compliance. All input signals are specified with t
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets.
A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements.
t
t
t
27
28
29
CONVST A,
CONVST A,
CONVST A,
CONVST A,
FRSTDATA
CONVST B
CONVST B
CONVST B
CONVST B
DB[15:0]
RESET
RESET
DATA:
BUSY
BUSY
CS
CS
RD
CS
Min
INVALID
t
Limit at T
t
8
13
t
24
t
t
26
t
7
7
Typ
t
t
t
RESET
RESET
10
t
t
Figure 3. CONVST Timing—Reading During a Conversion
5
5
MIN
Figure 2. CONVST Timing—Reading After a Conversion
V1
Figure 4. Parallel Mode, Separate CS and RD Pulses
, T
MAX
Max
19
24
17
22
24
t
t
1
1
t
t
11
27
V2
Unit
ns
ns
ns
ns
ns
Rev. B | Page 8 of 32
Description
Delay from RD falling edge to FRSTDATA low
V
V
Delay from 16
V
V
Delay from CS rising edge until FRSTDATA three-state enabled
V3
t
14
DRIVE
DRIVE
DRIVE
DRIVE
= 3.3 V to 5.25 V
= 2.3 V to 2.7 V
= 3.3 V to 5.25 V
= 2.3 V to 2.7 V
t
t
t
t
CYCLE
CYCLE
CONV
CONV
V4
t
t
3
3
R
= t
th
F
= 5 ns (10% to 90% of V
SCLK falling edge to FRSTDATA low
t
6
V7
t
15
t
4
DRIVE
V8
) and timed from a voltage level of 1.6 V.
t
t
t
16
17
29
t
9
t
t
2
2
Data Sheet

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