AD9644

Manufacturer Part NumberAD9644
Description14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
ManufacturerAnalog Devices
AD9644 datasheet
 


Specifications of AD9644

Resolution (bits)14bit# Chan2
Sample Rate155MSPSAnalog Input TypeDiff-Bip
Ain Range1.75 V p-pAdc ArchitecturePipelined
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Data Sheet
FEATURES
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz and 80 MSPS
SNR = 71.7 dBFS at 70 MHz and 155 MSPS
SFDR = 92 dBc at 70 MHz and 80 MSPS
SFDR = 92 dBc at 70 MHz and 155 MSPS
Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual
Serial Output Analog-to-Digital Converter (ADC)
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9644
VIN+A
VIN–A
VCMA
VIN+B
VIN–B
VCMB
REFERENCE
PDWN
PRODUCT HIGHLIGHTS
1.
An on-chip PLL allows users to provide a single ADC
sampling clock; the PLL multiplies the ADC sampling
clock to produce the corresponding JESD204A data rate
clock.
2.
The configurable JESD204A output block supports up to
1.6 Gbps per channel data rate when using a dedicated
data link per ADC or 3.2 Gbps data rate when using a
single shared data link for both ADCs.
3.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 250 MHz.
4.
Operation from a single 1.8 V power supply.
5.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding),
controlling the clock DCS, power-down, test modes,
voltage reference mode, and serial output configuration.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9644
AGND
DRVDD
DRGND
DOUT+A
14
DOUT–A
PIPELINE
14-BIT ADC
DSYNC+A
DSYNC–A
DOUT+B
14
DOUT–B
PIPELINE
14-BIT ADC
DSYNC+B
DSYNC–B
PLL
SERIAL PORT
1 TO 8
(SPI)
CLOCK
DIVIDER
SCLK SDIO CSB
CLK+ CLK–
SYNC
Figure 1. 48-Lead 7 mm × 7 mm LFCSP
www.analog.com
©2010–2012 Analog Devices, Inc. All rights reserved.

AD9644 Summary of contents

  • Page 1

    ... DCS, power-down, test modes, voltage reference mode, and serial output configuration. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9644 AGND DRVDD DRGND DOUT+A 14 DOUT–A ...

  • Page 2

    ... AD9644 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 ADC DC Specifications ............................................................... 4 ADC AC Specifications ............................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 8 Timing Specifications .................................................................. 9 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ................................................................ 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 13 Equivalent Circuits ......................................................................... 19 Theory of Operation ...

  • Page 3

    ... Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9644 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. Rev Page ...

  • Page 4

    ... Rev Page Data Sheet AD9644-155 Typ Max Unit Bits Guaranteed ±2.2 ±11 mV −1 FSR ±0.55 LSB ±0.3 LSB ±1.25 LSB ±0.55 LSB +1 +0. FSR ±2 ppm/°C ±144 ppm/°C ...

  • Page 5

    ... MHz MHz 180 MHz IN AD9644BCPZ-80 AD9644CCPZ-80 AD9644BCPZ-155 f = 220 MHz IN WORST OTHER (HARMONIC OR SPUR MHz MHz 180 MHz IN AD9644BCPZ-80 AD9644CCPZ-80 AD9644BCPZ-155 f = 220 MHz IN AD9644-80 Temperature Min Typ Max 25°C 73.8 25°C 73.7 25°C 72.6 Full 71.8 Full 70.0 Full 25°C 72.0 25°C 72.7 25° ...

  • Page 6

    ... Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. 3 Analog input bandwidth specifies the −3 dB input BW of the AD9644 input. The usable full-scale BW of the part with good performance is 250 MHz. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted ...

  • Page 7

    ... Full −92 Full −10 Full 26 Full 2 CMOS Full 1.22 Full 0 Full −10 Full 38 Full 26 Full 5 Full CML Full 0.6 0.8 Full 0.75 DRVDD/2 Rev Page AD9644 Max Unit 2.1 V 0.6 V +10 µA 132 µA kΩ pF 2.1 V 0.6 V −135 µA +10 µA kΩ pF 2.1 V 0.6 V +10 µA 128 µA kΩ ...

  • Page 8

    ... Full 23 25°C 1.6 25°C 40 25°C 9.5 25°C 5.2 25°C 50 25°C 100 25°C 2 Rev Page Data Sheet AD9644-155 Max Min Typ Max 640 640 80 40 155 6.45 8.75 1.935 3.225 4.515 6.55 3.065 3.225 3.385 0.8 0.78 0.125 1/(20 × CLK 50 ...

  • Page 9

    ... ENCODED INTO 2 ENCODED INTO 2 8b/10b SYMBOLS 8b/10b SYMBOLS Figure 2. Data Output Timing t t SSYNC HSYNC Figure 3. SYNC Input Timing Requirements Rev Page AD9644 Limit 0.30 ns typ 0.30 ns typ 2 ns min 2 ns min 40 ns min 2 ns min 2 ns min 10 ns min 10 ns min ...

  • Page 10

    ... AD9644 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCMA, VCMB to AGND CSB to AGND SCLK to AGND SDIO to AGND PDWN to AGND DOUT+A, DOUT0−A, DOUT0+B, DOUT−B to AGND DSYNC+A, DSYNC− ...

  • Page 11

    ... Active Low JESD204A LVDS Channel A SYNC Input—Complement. Input Active Low JESD204A LVDS Channel B SYNC Input—True/JESD204A CMOS Channel A SYNC Input. Input Active Low JESD204A LVDS Channel B SYNC Input—Complement. Rev Page VCMA 35 DNC 34 DNC 33 PDWN 32 DNC 31 CSB 30 SCLK 29 SDIO 28 DRVDD 27 DRVDD 26 DRGND 25 DNC AD9644 ...

  • Page 12

    ... AD9644 Pin No. Mnemonic Digital Outputs 20 DOUT+A 19 DOUT−A 18 DOUT+B 17 DOUT−B SPI Control 30 SCLK 29 SDIO 31 CSB ADC Configuration 33 PDWN Type Description Output Channel A CML Output Data—True. Output Channel A CML Output Data—Complement. Output Channel B CML Output Data—True. Output Channel B CML Output Data—Complement. ...

  • Page 13

    ... MHz Figure 8. AD9644-80 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 30.1 MHz Figure 9. AD9644-80 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 70.1 MHz Figure 10. AD9644-80 Single-Tone FFT with f IN Rev Page 80MSPS 140.3MHz @ – ...

  • Page 14

    ... Figure 14. AD9644-80 Single-Tone SNR/SFDR vs. Input Frequency ( –20 –40 –60 –80 –100 –120 –90 ) Figure 15. AD9644-80 Two-Tone SFDR/IMD3 vs. Input Amplitude ( –20 –40 –60 –80 –100 –120 200 250 –90 ) and Figure 16. AD9644-80 Two-Tone SFDR/IMD3 vs. Input Amplitude ( MSPS S Rev ...

  • Page 15

    ... IN2 100 95 90 SNR CHANNEL B SFDR CHANNEL B 85 SNR CHANNEL A SFDR CHANNEL SAMPLE RATE (MSPS) Figure 19. AD9644-80 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 70. MHz IN 14,000 12,000 10,000 32.9 MHz IN2 –0.2 –0.4 –0.6 –0.8 –1 169.1 MHz and IN1 0 ...

  • Page 16

    ... MHz Figure 26. AD9644-155 Single-Tone FFT with –20 –40 THIRD –60 HARMONIC –80 –100 –120 –140 0 = 30.1 MHz Figure 27. AD9644-155 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 0 = 70.1 MHz Figure 28. AD9644-155 Single-Tone FFT with f IN Rev Page Data Sheet 155MSPS 140.1MHz @ – ...

  • Page 17

    ... Temperature with 1.75 V p-p Full-Scale, f –30 –20 – Figure 32. AD9644-155 Single-Tone SNR/SFDR vs. Input Frequency (f IN –30 –20 – Figure 33. AD9644-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN 200 250 300 ) and Figure 34. AD9644-155 Two-Tone SFDR/IMD3 vs. Input Amplitude ( MSPS S Rev Page 100 SNR @ –40°C SFDR @ – ...

  • Page 18

    ... Figure 36. AD9644-155 Two-Tone FFT with 172.1 MHz IN2 100 110 SAMPLE RATE (MSPS) Figure 37. AD9644-155 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 70. MHz IN 4000 3500 3000 2500 2000 1500 1000 = 32.9 MHz IN2 –0.2 –0.4 –0.6 –0.8 = 169 ...

  • Page 19

    ... Rev Page 350Ω SCLK OR 30kΩ PDWN Figure 45. Equivalent SCLK or PDWN Input Circuit AVDD 30kΩ 350Ω CSB Figure 46. Equivalent CSB Input Circuit AVDD AVDD DSYNC±A/B 0.9V OR SYNC 16kΩ 0.9V Figure 47. Equivalent SYNC and DSYNC Input Circuit AD9644 ...

  • Page 20

    ... MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. In nondiversity applications, the AD9644 can be used as a base- band or direct downconversion receiver, in which one ADC is used for I input data, and the other is used for Q input data. ...

  • Page 21

    ... ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9644 (see Figure 49), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. ...

  • Page 22

    ... MSPS, dynamic performance of the AD9644 can degrade. Figure 54 and Figure 55 show two preferred methods for clocking the AD9644 (at clock rates up to 640 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun transformer. ...

  • Page 23

    ... AD9644 to produce the result shown. 0.1µF The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9644. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...

  • Page 24

    ... PDWN pin high), the AD9644 is placed in power-down mode. In this state, the ADC typically dissipates 15 mW. During power- down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9644 to its normal operating mode. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, clock, and JESD204A outputs ...

  • Page 25

    ... Table 10 via a quick configuration register at Address 0x5E accessible via the SPI bus. In addition to the default mode, the user can program the AD9644 to output both ADC channels on a single lane (F = 4). This mode allows use of a single high speed data lane, which simplifies board layout and connector requirements ...

  • Page 26

    ... AD9644 transmits the K28.5 comma symbol until the receiver achieves synchronization. The receiver should then deassert the sync signal (take DSYNC high) and the AD9644 begins the initial lane alignment sequence (when enabled through Bits[3:2] of Address 0x60) and subsequently begins transmitting sample data ...

  • Page 27

    ... Data Sheet Table 11. AD9644 JESD204A Frame Alignment Monitoring and Correction Replacement Characters Scrambling Lane Synchronization Off On Off On Off Off Off Frame and Lane Alignment Monitoring and Correction Frame alignment monitoring and correction is part of the JESD204A specification. The 14-bit word requires two octets to transmit all the data ...

  • Page 28

    ... TIME (ps) Figure 69. AD9644-155 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations Figure 68 and Figure 69 shows an example of the digital output (default) data eye and a time interval error (TIE) jitter histogram. Additional SPI options allow the user to further increase the output driver voltage swing of all four outputs to drive longer trace lengths (see Address 0x15 in Table 17) ...

  • Page 29

    ... Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 13 for the initial values) and that the AD9644 inverts the bit stream with relation to the ITU-T standard. Table 13. PN Sequence ...

  • Page 30

    ... AD9644 Table 14. Flexible Output Test Modes from SPI Register 0x0D Output Test Mode Bit Sequence Pattern Name 0000 Off (default) 0001 Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checkerboard 0101 PN sequence long 0110 PN sequence short 0111 One-/zero-word toggle ...

  • Page 31

    ... Data Sheet SERIAL PORT INTERFACE (SPI) The AD9644 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

  • Page 32

    ... SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9644 part-specific features are described in detail in the Memory Map Register Descriptions section. Table 16. Features Accessible Using the SPI Feature Name ...

  • Page 33

    ... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD9644 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17. Logic Levels An explanation of logic level terminology follows: • ...

  • Page 34

    ... Locked 0x0B Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0] (AD9644 = 0x7E) (default) Speed grade ID Open Open MSPS 10 = 155 MSPS Open Open Open Open Open Open Open Open External power- Open ...

  • Page 35

    ... Open Open 0x00 AD9644 Default/ Comments When this register is set, test data is used in place of normal ADC data Configures outputs and the format of the data Full-scale input adjustment in 0 ...

  • Page 36

    ... AD9644 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x3A Sync control Open Open (global) JESD204A Configuration Registers 0x5E JESD204A Open Open quick configure (global) 0x5F JESD204A Open Open lane assignment (global) ...

  • Page 37

    ... Total bits per sample (N’) (read only) Open Samples per converter (S) frame cycle (read only) Always 1 for the AD9644 Open Number of control words per frame clock cycle per Link (CF) – always 0 for the AD9644 (read only) Rev Page AD9644 Default Bit 0 Value ...

  • Page 38

    ... AD9644 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x76 JESD204A Serial Reserved Field 1 (RES1) – these registers are available for customer use serial reserved Field 1 (RES1) 0x77 JESD204A Serial Reserved Field 2 (RES2) – these registers are available for customer use serial reserved ...

  • Page 39

    ... programmed the ILAS does not repeat programmed the ILAS repeat one time and so on. See Register 0x60, Bits[3:2] to enable the ILAS and for a test mode to continuously enable the initial lane alignment sequence. Rev Page AD9644 ...

  • Page 40

    ... JESD204A HD and CF Configuration (Register 0x75) Bit 7—Enable High Density Format (Read Only) Read only bit—always 0 in the AD9644. Bits[6:5]—Reserved Bits[4:0]—Number of Control Words per Frame Clock Cycle per Link (CF) Read only bits—reads back 0x0 for the AD9644. Rev Page Data Sheet ...

  • Page 41

    ... Sum (all link configuration parameters for Lane 0) mode 256. JESD204A Serial Checksum Value for Lane 1 (Register 0x79) Bits[7:0]—Serial Checksum Value for Lane 1 This read only register is automatically calculated for each lane. Sum (all link configuration parameters for Lane 1) mode 256. Rev Page AD9644 ...

  • Page 42

    ... AD9644 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9644 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. Power and Ground Recommendations When connecting power to the AD9644 recommended that two separate 1 ...

  • Page 43

    ... AD9644BCPZ-80 −40°C to +85°C AD9644BCPZRL7-80 −40°C to +85°C AD9644CCPZ-80 −40°C to +85°C AD9644CCPZRL7-80 −40°C to +85°C AD9644BCPZ-155 −40°C to +85°C AD9644BCPZRL7-155 −40°C to +85°C AD9644-80KITZ AD9644-155KITZ RoHS Compliant Part. 7.10 0.60 MAX 7.00 SQ 6.90 0.60 MAX 0.50 6.85 REF 6. ...

  • Page 44

    ... AD9644 NOTES ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09180-0-1/12(C) Rev Page Data Sheet ...