AD9644 Analog Devices, AD9644 Datasheet - Page 22

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AD9644

Manufacturer Part Number
AD9644
Description
14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9644

Resolution (bits)
14bit
# Chan
2
Sample Rate
155MSPS
Analog Input Type
Diff-Bip
Ain Range
1.75 V p-p
Adc Architecture
Pipelined
AD9644
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9644.
The input full scale range can be adjusted through the SPI port by
adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be
used to change the full scale between 1.383 V p-p and 2.087 V p-p
in 0.022 V steps, as shown in Table 17.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9644 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins by
means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 53) and require no
external bias. If the inputs are floated, the CLK− pin is pulled low
to prevent inadvertent clocking.
Clock Input Options
The AD9644 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section. The
minimum conversion rate of the AD9644 is 40 MSPS. At clock
rates below 40 MSPS, dynamic performance of the AD9644 can
degrade.
Figure 54 and Figure 55 show two preferred methods for clocking
the AD9644 (at clock rates up to 640 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 640 MHz, and the RF transformer is recom-
mended for clock frequencies from 40 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
CLK+
Figure 52. Differential Input Configuration Using the AD8376 (Filter Values Shown Are for a 20 MHz Bandwidth Filter Centered at 140 MHz)
Figure 53. Equivalent Clock Input Circuit
2pF
AVDD
0.9V
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
AD8376
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
1µH
1µH
2pF
1000pF
1000pF
CLK–
VPOS
1nF
301Ω
180nH
180nH
Rev. C | Page 22 of 44
5.1pF
220nH
220nH
3.9pF
165Ω
165Ω
secondary limit clock excursions into the AD9644 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9644 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 56. The
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520
/AD9522
CLOCK
CLOCK
CLOCK
INPUT
INPUT
INPUT
CLOCK
VCM
15pF
1nF
INPUT
Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)
50kΩ
Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)
Figure 56. Differential PECL Sample Clock (Up to 640 MHz)
68nH
clock drivers offer excellent jitter performance.
50Ω
0.1µF
50Ω
1nF
AD9644
0.1µF
0.1µF
50kΩ
1nF
100Ω
ADT1-1WT, 1:1Z
Mini-Circuits
AD95xx
PECL DRIVER
XFMR
0.1µF
240Ω
®
0.1µF
0.1µF
0.1µF
0.1µF
AD9510/AD9511/AD9512/
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
240Ω
0.1µF
0.1µF
100Ω
Data Sheet
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
ADC
ADC
ADC

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