AD9644 Analog Devices, AD9644 Datasheet - Page 24

• Manufacturer Part Number: AD9644
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9644

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 155MSPS
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined

AD9644
CHANNEL/CHIP SYNCHRONIZATION
The AD9644 has a SYNC input that offers the user flexible
synchronization options for synchronizing the clock divider.
The clock divider sync feature is useful for guaranteeing synchro-
nized sample clocks across multiple ADCs. The input clock
divider can be enabled to synchronize on a single occurrence of
the SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally syn-
chronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 60 and Figure 61, the power dissipated by
the AD9644 varies with its sample rate (AD9644-80 shown).
The data in Figure 60 and Figure 61 was taken in JESD204A
serial output mode, using the same operating conditions as those
used for the Typical Performance Characteristics.
Figure 60. AD9644-80 Power and Current vs. Encode Frequency with f
0.5
0.4
0.3
0.2
0.1
0.60
0.50
0.40
0.30
0.20
0.10
0
Figure 61. AD9644-155 Power and Current vs. Encode Frequency
40
0
80
TOTAL POWER
90
50
TOTAL POWER
ENCODE FREQUENCY (MSPS)
100
ENCODE FREQUENCY (MSPS)
IDRVDD
I
IAVDD
AVDD
with f
110
I
DRVDD
10.1 MHz
IN
60
= 10.1 MHz
120
130
70
140
150
80
0.25
0.20
0.15
0.10
0.05
0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
IN
Rev. C | Page 24 of 44
=
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9644 is placed in power-down mode.
In this state, the ADC typically dissipates 15 mW. During power-
down, the output drivers are placed in a high impedance state.
Asserting the PDWN pin low returns the AD9644 to its normal
operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
clock, and JESD204A outputs . Internal capacitors are discharged
when entering power-down mode and then must be recharged
when returning to normal operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered and
the JESD204A outputs running when faster wake-up times are
required.
DIGITAL OUTPUTS
JESD204A Transmit Top Level Description
The AD9644 digital output complies with the JEDEC Standard
No. 204A (JESD204A), which describes a serial interface for
data converters. JESD204A uses 8B/10B encoding as well as
optional scrambling. K28.5 and K28.7 comma symbols are used
for frame synchronization and the K28.3 control symbol is used
for lane synchronization. The receiver is required to lock onto
the serial data stream and recover the clock with the use of a
PLL. For details on the output interface, users are encouraged to
refer to the JESD204A standard.
The JESD204A transmit block is used to multiplex data from
the two analog-to-digital converters onto two independent
JESD204A Links. Each JESD204A Link is considered a separate
instance of the JESD204A specification, has an independent
DSYNC signal, and contains one or more lanes. Note that the
JESD204 specification only allows one lane per link, while the
JESD204A specification adds multilane support through an
alignment procedure.
Each JESD204A Link is described according to the following
nomenclature:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S = samples transmitted/single converter/frame cycle
M = number of converters/converter device (link)
L = number of lanes/converter device (link)
N = converter resolution
N’ = total number of bits per sample
CF = number of control words/frame clock cycle/converter
device (link)
CS = number of control bits/conversion sample
K = number of frames per multiframe
HD = high density mode
F = octets/frame
C = control bit (overrange, overflow, underflow)
T = tail bit
SCR = scrambler enable/disable
FCHK = checksum
Data Sheet