AD9644 Analog Devices, AD9644 Datasheet - Page 34

• Manufacturer Part Number: AD9644
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9644

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 155MSPS
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined

AD9644
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0A
0x0B
Register
Name
SPI port
configuration
(global)
Chip ID
(global)
Chip grade
(global)
Channel index
(global)
Transfer
(global)
Power modes
(local)
Global clock
(global)
PLL status
(global)
Clock divide
(global)
1
Bit 7
(MSB)
0
Open
Open
Open
Open
Open
PLL
Locked
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
Open
External power-
down pin
function (local)
0 = power-
down
1 = standby
Open
Open
Input clock divider phase adjust
Speed grade ID
10 = 155 MSPS
00 = 80 MSPS
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
001 = 1 input clock cycle
000 = no delay
Bit 4
1
Open
Open
Open
Open
Open
Rev. C | Page 34 of 44
8-bit chip ID[7:0]
(AD9644 = 0x7E)
(default)
Bit 3
1
Open
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Open
Open
Bit 1
LSB first
Open
ADC B and
Link B
(default)
Open
Open
Open
Internal power-down mode
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
00 = normal operation
01 = full power-down
11 = reserved
10 = standby
(local)
Bit 0
(LSB)
0
Open
ADC A and
Link A
(default)
Transfer
Duty cycle
stabilizer
(default)
Open
Default
Value
(Hex)
0x18
0x7E
0x03
0x00
0x00
0x01
0x00
0x00
Data Sheet
Default/
Comments
Nibbles are
mirrored so
that LSB-first
or MSB-first
mode is set
correctly,
regardless of
shift mode.
To control
this register,
all channel
index bits in
Register
0x05 must
be set.
Read only
Speed grade
ID
differentiates
devices;
read only
Bits set to
determine
which
device on
the chip
receives
next write
command;
local
registers
only
Synchro-
nously
transfers
data from
master shift
register to
slave
Determines
various
generic
modes of
chip
operation
Read Only
Clock divide
values other
than 000
automatically
causes duty
cycle
stabilizer to
become
active