AD9650

Manufacturer Part NumberAD9650
Description16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
ManufacturerAnalog Devices
AD9650 datasheet
 


Specifications of AD9650

Resolution (bits)16bit# Chan2
Sample Rate105MSPSInterfaceLVDS,Par
Analog Input TypeDiff-BipAin Range(2Vref) p-p,2.7 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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Data Sheet
FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
SNR
82 dBFS at 30 MHz input and 105 MSPS data rate
83 dBFS at 9.7 MHz input and 25 MSPS data rate
SFDR
90 dBc at 30 MHz input and 105 MSPS data rate
95 dBc at 9.7 MHz input and 25 MSPS data rate
Low power
328 mW per channel at 105 MSPS
119 mW per channel at 25 MSPS
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
Analog input range of 2.7 V p-p
Optional on-chip dither
Integrated ADC sample-and-hold inputs
Differential analog inputs with 500 MHz bandwidth
ADC clock duty cycle stabilizer
APPLICATIONS
Industrial instrumentation
X-Ray, MRI, and ultrasound equipment
High speed pulse acquisition
Chemical and spectrum analysis
Direct conversion receivers
Multimode digital receivers
Smart antenna systems
General-purpose software radios
GENERAL DESCRIPTION
The
AD9650
is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/
105 MSPS analog-to-digital converter (ADC) designed for
digitizing high frequency, wide dynamic range signals with
input frequencies of up to 300 MHz.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold
analog input amplifiers, and shared integrated voltage reference,
which eases design considerations. A duty cycle stabilizer is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converters to maintain excellent performance.
The ADC output data can be routed directly to the two external
16-bit output ports or multiplexed on a single 16-bit bus. These
outputs can be set to either 1.8 V CMOS or LVDS.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS,
1.8 V Dual Analog-to-Digital Converter (ADC)
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9650
VIN+A
VIN–A
VREF
SENSE
REF
SELECT
VCM
RBIAS
VIN–B
VIN+B
MULTICHIP
SYNC
AGND
SYNC
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The
AD9650
is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
On-chip dither option for improved SFDR performance
with low power analog input.
2.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and test modes.
5.
Pin compatible with the AD9268 and other dual families,
AD9269, AD9251, AD9231, and AD9204. This allows a
simple migration across resolutions and bandwidth.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9650
SDIO/
SCLK/
CSB
DRVDD
DCS
DFS
SPI
ORA
PROGRAMMING DATA
D15A (MSB)
16
CMOS/LVDS
ADC
TO
OUTPUT BUFFER
D0A (LSB)
CLK+
DIVIDE 1
TO 8
CLK–
DCOA
DUTY CYCLE
DCO
STABILIZER
GENERATION
DCOB
ORB
D15B (MSB)
16
CMOS/LVDS
TO
ADC
OUTPUT BUFFER
D0B (LSB)
PDWN
OEB
Figure 1.
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.

AD9650 Summary of contents

  • Page 1

    ... Pin compatible with the AD9268 and other dual families, AD9269, AD9251, AD9231, and AD9204. This allows a simple migration across resolutions and bandwidth. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9650 SDIO/ SCLK/ CSB DRVDD DCS DFS SPI ...

  • Page 2

    ... Timing Specifications .................................................................. 8 Absolute Maximum Ratings .......................................................... 10 Thermal Characteristics ............................................................ 10 ESD Caution ................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 AD9650-25 .................................................................................. 15 AD9650-65 .................................................................................. 18 AD9650-80 .................................................................................. 21 AD9650-105 ................................................................................ 24 Equivalent Circuits ......................................................................... 28 Theory of Operation ...................................................................... 29 REVISION HISTORY 1/11—Rev Rev. A Changes to Table 17 ........................................................................ 40 7/10—Revision 0: Initial Version ADC Architecture ...................................................................... 29 Analog Input Considerations ................................................... 29 Voltage Reference ...

  • Page 3

    ... AD9650 Unit Bits % FSR % FSR LSB LSB LSB LSB % FSR % FSR ppm/°C ppm/° LSB rms V p kΩ ...

  • Page 4

    ... Rev Page Data Sheet AD9650BCPZ-80 AD9650BCPZ-105 Min Typ Max Min Typ Max 83 82 81.6 80 80.4 80.7 80 78.5 78.8 75.1 75.5 13.5 13.3 13.2 13.2 13.0 13.0 13 ...

  • Page 5

    ... Full 26 Full 2 Full 1.22 Full 0 Full −10 Full 38 Full 26 Full 5 Full 1.22 Full 0 Full −90 Full −10 Full 26 Full 5 Rev Page AD9650 Max Unit V 3.6 V p-p AVDD V 1.4 V +100 µA +100 µ kΩ V AVDD V AVDD V 0.6 V +100 µA +100 µ kΩ ...

  • Page 6

    ... AD9650 Parameter DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage µ 0 Low Level Output Voltage µA OL LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (V ), ANSI Mode OD Output Offset Voltage (V ), ANSI Mode OS Differential Output Voltage (V ), Reduced Swing Mode ...

  • Page 7

    ... Min Typ Max Min Typ 640 12.5 9.5 3.75 6.25 8.75 2.85 4.75 5.95 6.25 6.55 4.5 4.75 0.8 0.8 1.0 1.0 0.080 0.075 2.8 3.5 4.2 2.8 3.5 3.1 3.1 −0.6 −0.4 0 −0.6 −0.4 2.9 3.7 4.5 2.9 3.7 3.9 3.9 −0.1 +0.2 +0.5 −0.1 +0 12/12.5 12/12.5 500 500 2 2 AD9650 Max Unit 640 MHz 105 MSPS 105 MSPS ns 6. rms 4 4 +0.5 ns Cycles Cycles µs Cycles ...

  • Page 8

    ... AD9650 TIMING SPECIFICATIONS Table 5. Parameter Conditions SYNC TIMING REQUIREMENTS t SYNC to rising edge of CLK+ setup time SSYNC t SYNC to rising edge of CLK+ hold time HSYNC SPI TIMING REQUIREMENTS 1 t Setup time between the data and the rising edge of SCLK DS t Hold time between the data and the rising edge of SCLK ...

  • Page 9

    ... N – – – 11 Figure 4. LVDS Mode Data Output Timing t t SSYNC HSYNC Figure 5. SYNC Input Timing Requirements Rev Page – – – – – 8 AD9650 ...

  • Page 10

    ... AD9650 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical 1 AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B Through D15A/D15B to ...

  • Page 11

    ... Channel A CMOS Output Data (LSB). Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Output Channel A CMOS Output Data. Rev Page AD9650 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS 44 SDIO/DCS 43 ORA 42 ...

  • Page 12

    ... AD9650 Pin No. Mnemonic 33 D7A 34 D8A 35 D9A 36 D10A 38 D11A 39 D12A 40 D13A 41 D14A 42 D15A 43 ORA 4 D0B 5 D1B 6 D2B 7 D3B 8 D4B 9 D5B 11 D6B 12 D7B 13 D8B 14 D9B 15 D10B 16 D11B 17 D12B 18 D13B 20 D14B 21 D15B 22 ORB 24 DCOA 23 DCOB SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN ...

  • Page 13

    ... Channel A/Channel B LVDS Output Data 1—True. Output Channel A/Channel B LVDS Output Data 1—Complement. Output Channel A/Channel B LVDS Output Data 2—True. Output Channel A/Channel B LVDS Output Data 2—Complement. Output Channel A/Channel B LVDS Output Data 3—True. Rev Page AD9650 48 PDWN 47 OEB 46 CSB 45 SCLK/DFS 44 ...

  • Page 14

    ... AD9650 Pin No. Mnemonic 11 D3− 14 D4+ 13 D4− 16 D5+ 15 D5− 18 D6+ 17 D6− 21 D7+ 20 D7− 23 D8+ 22 D8− 27 D9+ 26 D9− 30 D10+ 29 D10− 32 D11+ 31 D11− 34 D12+ 33 D12− 36 D13+ 35 D13− 39 D14+ 38 D14− 41 D15+ 40 D15− ...

  • Page 15

    ... MHz Figure 11. AD9650-25 Single-Tone FFT with 30.3 MHz Figure 12. AD9650-25 Single-Tone FFT with 70.1 MHz Figure 13. AD9650-25 Single-Tone SNR/SFDR vs. Input Amplitude (A IN Rev Page 25MSPS 9.7MHz @ –6dBFS SNR = 77.9dB (83.9dBFS) –20 SFDR = 99dBc –40 –60 –80 –100 – ...

  • Page 16

    ... SNR (–40°C) 75 SNR (+25°C) SNR (+85°C) SFDR (–40°C) 70 SFDR (+25°C) SFDR (+85° 100 150 200 INPUT FREQUENCY (MHz) Figure 15. AD9650-25 Single-Tone SNR/SFDR vs. Input Frequency (f with 2.7 V p-p Full Scale 105 100 95 SFDR (dBc SNR (dBFS SAMPLE RATE (MSPS) Figure 16 ...

  • Page 17

    ... TOTAL POWER LVDS (mW) 300 250 TOTAL POWER CMOS (mW) 200 LVDS AND CMOS I 150 100 SAMPLE RATE (MSPS) Figure 20. AD9650-25 Power and Current vs. Sample Rate (mA) AVDD LVDS I (mA) DRVDD CMOS I (mA) DRVDD Rev Page AD9650 ...

  • Page 18

    ... FREQUENCY (MHz) Figure 23. AD9650-65 Single-Tone FFT with f 0 –20 –40 –60 –80 –100 –120 –140 9.7 MHz Figure 24. AD9650-65 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 Figure 25. AD9650-65 Single-Tone FFT with f = 30.3 MHz IN 0 –20 – ...

  • Page 19

    ... SNR (dBFS SFDR (dBc –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 27. AD9650-65 Single-Tone SNR/SFDR vs. Input Amplitude (A with f =30.3 MHz IN 120 SFDR (dBFS) DITHER ON 115 110 105 100 95 SFDR (dBFS) DITHER OFF 90 SNR (dBFS) DITHER OFF 85 SNR (dBFS) DITHER ON ...

  • Page 20

    ... Rev Page 700 TOTAL POWER LVDS (mW) 600 500 400 TOTAL POWER CMOS (mW) 300 LVDS AND CMOS I AVDD 200 CMOS I LVDS I (mA) 100 DRVDD SAMPLE RATE (MSPS) Figure 34. AD9650-65 Power and Current vs. Sample Rate Data Sheet (mA) (mA) DRVDD 95 105 ...

  • Page 21

    ... 30.3 MHz Figure 39. AD9650-80 Single-Tone FFT with f IN 80MSPS 70.1MHz @ –1dBFS SNR = 80dB (81dBFS) SFDR = 86.4dBc Figure 40. AD9650-80 Single-Tone FFT with f = 70.1 MHz IN Rev Page 80MSPS 141MHz @ –1dBFS SNR = 79.3dB (80.3dBFS) –20 SFDR = 79.2dBc –40 –60 –80 –100 – ...

  • Page 22

    ... Rev Page 105 100 95 SFDR 90 85 SNR SAMPLE RATE (MSPS) Figure 44. AD9650-80 Single-Tone SNR/SFDR vs. Sample Rate (f with MHz IN 800000 900000 600000 200000 0 OUTPUT CODE Figure 45. AD9650-80 Grounded Input Histogram 6 DITHER DISABLED DITHER ENABLED –2 – ...

  • Page 23

    ... TOTAL POWER 700 600 500 TOTAL POWER CMOS (mW) 400 LVDS AND CMOS I 300 200 LVDS I CMOS I (mA) DRVDD 100 SAMPLE RATE (MSPS) Figure 48. AD9650-80 Power and Current vs. Sample Rate AD9650 LVDS (mW) (mA) AVDD (mA) DRVDD 105 115 125 ...

  • Page 24

    ... FREQUENCY (MHz) Figure 51. AD9650-105 Single-Tone FFT with f 0 –20 –40 –60 –80 –100 –120 –140 9.7 MHz Figure 52. AD9650-105 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 30.3 MHz Figure 53. AD9650-105 Single-Tone FFT with –20 – ...

  • Page 25

    ... SNR (dBFS) DITHER –100 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 56. AD9650-105 Single Tone SNR/SFDR vs. Input Amplitude (A with f = 30.3 MHz with and Without Dither Enabled IN 100 SNR (–40°C) 75 SFDR (–40°C) SNR (+25°C) SFDR (+25°C) 70 SNR (+85° ...

  • Page 26

    ... SFDR (dBFS) –100 –120 IMD3 (dBFS) –140 –90 –80 –70 –60 –50 –40 INPUT AMPLITUDE (dBFS) Figure 62. AD9650-105 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 128.3 MHz 124.8 MHz, f IN1 IN2 900 TOTAL POWER LVDS (mW) 800 TOTAL POWER CMOS (mW) 700 600 500 ...

  • Page 27

    ... Data Sheet 100 TYPICAL V CM SNR (dBFS) 90 SFDR (dBc 0.80 0.85 0.90 0.95 1.00 1.05 COMMON-MODE VOLTAGE (V) Figure 67. SNR/SFDR vs. Input Common Mode (VCM) with f = 30.3 MHz IN 1.10 1.15 1.20 Rev Page AD9650 ...

  • Page 28

    ... AD9650 EQUIVALENT CIRCUITS VIN±x Figure 68. Equivalent Analog Input Circuit AVDD 0.9V 10kΩ 10kΩ CLK+ Figure 69. Equivalent Clock Input Circuit DRVDD PAD Figure 70. Digital Output DRVDD 350Ω SDIO/DCS Figure 71. Equivalent SDIO/DCS Circuit DRVDD 350Ω SCLK/DFS OR OEB Figure 72. Equivalent SCLK/DFS or OEB Input Circuit CLK– ...

  • Page 29

    ... AVDD). The VCM pin must be decoupled to ground by a 0.1 µF capacitor, as described in the Applications Information section. Rev Page AN-742 Application Note, Frequency BIAS PAR1 PAR2 PAR1 PAR2 S S BIAS Figure 77. Switched-Capacitor Input AD9650 are not internally dc biased. AD9650 AN-827 ...

  • Page 30

    ... ADC through the dither DAC is precisely subtracted out digitally to minimize SNR degradation. When dithering is enabled, the dither DAC is driven by a pseudorandom number generator (PN gen). In the AD9650, the dither DAC is precisely calibrated to result in only a very small degradation in SNR and SINAD. AD9650 ...

  • Page 31

    ... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9650. For applications in which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 81). In this configuration, the input is ac-coupled, and the CML is provided to each input through a 33 Ω ...

  • Page 32

    ... Internal Reference Connection A stable and accurate 1.35 V reference is built into the AD9650, allowing a 2.7 V p-p full-scale input. To configure the for an internal reference, the SENSE pin must be tied low. In addition, to achieve optimal noise performance recommended that the VREF pin be decoupled by 1.0 µ ...

  • Page 33

    ... OPTIONAL 0.1µF 1kΩ 100Ω 0.1µF AD951x CMOS DRIVER 1kΩ 50Ω 1 0.1µF contains an input clock divider with the ability to clock divider can be synchronized using the external AD9650 clock CLK+ ADC AD9650 CLK– CLK+ ADC AD9650 CLK– CLK+ ADC AD9650 ...

  • Page 34

    ... AD9650 family of parts. The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9650. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources ...

  • Page 35

    ... Data outputs are available one propagation delay (t The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9650. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the At clock rates below 10 MSPS, dynamic performance can degrade ...

  • Page 36

    ... A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9650. Various output test options are also provided to place predictable values on the outputs of the AD9650. ...

  • Page 37

    ... AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t CLK t LOW A11 A10 Figure 93. Serial Port Interface Timing Diagram Rev Page DON’T CARE AD9650 DON’T CARE ...

  • Page 38

    ... The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9650. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 39

    ... SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 17 affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Rev Page AD9650 ...

  • Page 40

    ... Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit Chip ID[7:0] (AD9650 = 0x3B, default) Speed grade ID Open Open 001 = 105 MSPS 010 = 80 MSPS 011 = 65 MSPS 100 = 25 MSPS Open Open Open Open Open Open Open ...

  • Page 41

    ... BIST signature[7:0] BIST signature[15:8] Open Dither Open Open enable Open Open Open Clock divider next SYNC only Rev Page AD9650 Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments 0x00 When this register is set, the test data is placed on the output pins in place of normal data ...

  • Page 42

    ... AD9650 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. SYNC Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next SYNC Only If the master SYNC enable bit (Address 0x100, Bit 0) and the clock ...

  • Page 43

    ... LVDS mode. This additional DRVDD current does not cause damage to the AD9650, but it should be taken into account when consid- ering the maximum DRVDD current for the part. To avoid this additional DRVDD current, the can be disabled at power-up by taking the OEB pin high ...

  • Page 44

    ... AD9650BCPZRL7-80 −40°C to +85°C AD9650BCPZ-105 −40°C to +85°C AD9650BCPZRL7-105 −40°C to +85°C AD9650-25EBZ AD9650-65EBZ AD9650-80EBZ AD9650-105EBZ Z = RoHS Compliant Part. 1 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...