AD9650 Analog Devices, AD9650 Datasheet - Page 33

• Manufacturer Part Number: AD9650
• Description: 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9650

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 105MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p,2.7 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
Clock Input Considerations
For optimum performance, the
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 86) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
Clock Input Options
The
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 87 and Figure 88 show two preferred methods for clocking
the
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun’s
secondary windings limit the clock excursions into the
to approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
CLOCK
INPUT
CLOCK
INPUT
AD9650
AD9650
Figure 87. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLK+
Figure 88. Balun-Coupled Differential Clock (Up to 625 MHz)
50Ω
0.1µF
(at clock rates up to 625 MHz). A low jitter clock
has a very flexible clock input structure. Clock input
50Ω
1nF
Figure 86. Equivalent Clock Input Circuit
1nF
9pF
100Ω
ADT1-1WT, 1:1Z
Mini-Circuits
0.1µF
XFMR
AVDD
0.9V
®
0.1µF
0.1µF
0.1µF
0.1µF
AD9650
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
sample clock inputs,
AD9650
9pF
CLK+
CLK–
AD9650
CLK+
CLK–
CLK–
AD9650
ADC
while
ADC
AD9650
Rev. A | Page 33 of 44
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 89. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518
drivers offer excellent jitter performance.
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 90. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518 clock drivers offer excellent jitter performance.
CLOCK
CLOCK
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor (see Figure 91).
CLOCK
Input Clock Divider
The
divide the input clock by integer values between 1 and 8. For
divide ratios of 1, 2, 4, or 8, the duty cycle stabilizer (DCS) is
optional. For other divide ratios, divide-by-3, -5, -6, and -7, the
duty cycle stabilizer must be enabled for proper part operation.
The
SYNC input. Bit 0 to Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
CLOCK
CLOCK
1
INPUT
INPUT
INPUT
INPUT
INPUT
50Ω RESISTOR IS OPTIONAL.
AD9650
AD9650
Figure 91. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
50kΩ
50kΩ
Figure 90. Differential LVDS Sample Clock (Up to 625 MHz)
Figure 89. Differential PECL Sample Clock (Up to 625 MHz)
50Ω
0.1µF
1
clock divider can be synchronized using the external
contains an input clock divider with the ability to
0.1µF
0.1µF
50kΩ
0.1µF
0.1µF
50kΩ
V
CC
1kΩ
1kΩ
AD951x
LVDS DRIVER
AD951x
PECL DRIVER
AD951x
CMOS DRIVER
240Ω
OPTIONAL
240Ω
0.1µF
0.1µF
100Ω
0.1µF
100Ω
0.1µF
0.1µF
100Ω
0.1µF
CLK+
CLK–
CLK+
CLK–
CLK+
CLK–
AD9650
AD9650
AD9650
AD9650
ADC
ADC
ADC
clock