AD9650 Analog Devices, AD9650 Datasheet - Page 41

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AD9650

Manufacturer Part Number
AD9650
Description
16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9650

Resolution (bits)
16bit
# Chan
2
Sample Rate
105MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Bip
Ain Range
(2Vref) p-p,2.7 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

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Data Sheet
Address
(Hex)
0x0D
0x0E
0x0F
0x10
0x14
0x16
0x17
0x24
0x25
0x30
Digital Feature Control
0x100
Register
Name
Test mode
(local)
BIST enable
(global)
ADC input
(global)
Offset adjust
(local)
Output
mode
Clock phase
control
(global)
DCO output
delay (global)
BIST signature
LSB (local)
BIST signature
MSB (local)
Dither
enable (local)
SYNC control
(global)
Bit 7
(MSB)
Open
Open
Open
Drive
strength
0 = ANSI
LVDS;
1 =
reduced
swing
LVDS
(global)
Invert
DCO
clock
Open
Open
Open
Bit 6
Open
Open
Open
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Open
Open
Open
Bit 5
Reset PN
long gen
Open
Open
CMOS
output
interleave
enable
(global)
Open
Open
Open
Open
Offset adjust in LSBs from +127 to −128
(twos complement format)
Bit 4
Reset
PN short
gen
Open
Open
Output
enable
bar
(local)
Open
Dither
enable
Open
BIST signature[15:8]
Rev. A | Page 41 of 44
BIST signature[7:0]
Bit 3
Open
Open
Open
(must be
written
low)
Open
Open
Open
Open
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
11110 = 2419 ps
11111 = 2500 ps
Bit 2
Reset BIST
sequence
Open
Output
invert
(local)
Clock
divider
next
SYNC
only
Open
Input clock divider phase adjust
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Open
Bit 1
Open
Open
Clock
divider
SYNC
enable
Output format
00 = offset binary
01 = twos
01 = gray code
11 = offset binary
(local)
complement
Bit 0
(LSB)
BIST
enable
Common-
mode
servo
enable
Master
SYNC
enable
Open
Default
Value
(Hex)
0x00
0x04
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Default
Notes/
Comments
When this
register is set,
the test data
is placed on
the output
pins in place of
normal data.
Configures the
outputs and
the format of
the data.
Allows
selection of
clock delays
into the input
clock divider.
Read only.
Read only.
AD9650

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