AD9650 Analog Devices, AD9650 Datasheet - Page 42

• Manufacturer Part Number: AD9650
• Description: 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9650

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 105MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p,2.7 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9650
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
SYNC Control (Register 0x100)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next SYNC Only
If the master SYNC enable bit (Address 0x100, Bit 0) and the clock
divider SYNC enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to synchronize to the first SYNC pulse it
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receives and to ignore the rest. The clock divider SYNC enable bit
(Address 0x100, Bit 1) resets after it synchronizes.
Bit 1—Clock Divider SYNC Enable
Bit 1 gates the SYNC pulse to the clock divider. The SYNC
signal is enabled when Bit 1 is high and Bit 0 is high. This is
continuous SYNC mode.
Bit 0—Master SYNC Enable
Bit 0 must be high to enable any of the SYNC functions. If the
SYNC capability is not used, this bit should remain low to
conserve power.
Data Sheet