AD9650 Analog Devices, AD9650 Datasheet - Page 5

• Manufacturer Part Number: AD9650
• Description: 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9650

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 105MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p,2.7 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, V
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
SYNC INPUT
LOGIC INPUT (CSB)
LOGIC INPUT (SCLK/DFS)
LOGIC INPUT/OUTPUT (SDIO/DCS)
LOGIC INPUTS (OEB, PDWN)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
Low Level Input Current
Input Resistance
Input Capacitance
1
2
2
IN
IN
= 1.8 V)
= 1.8 V)
1
IN
= −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled, unless
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. A | Page 5 of 44
Min
0.3
AGND
0.9
−100
−100
8
AGND
1.2
AGND
−100
−100
12
1.22
0
−10
40
1.22
0
−92
−10
1.22
0
−10
38
1.22
0
−90
−10
Typ
CMOS/LVDS/LVPECL
0.9
9
10
CMOS
0.9
1
16
26
2
26
2
26
5
26
5
Max
3.6
AVDD
1.4
+100
+100
12
AVDD
AVDD
0.6
+100
+100
20
2.1
0.6
+10
132
2.1
0.6
−135
+10
2.1
0.6
+10
128
2.1
0.6
−134
+10
AD9650
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
V
V
µA
µA
pF
kΩ
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF
V
V
µA
µA
kΩ
pF