AD9650 Analog Devices, AD9650 Datasheet - Page 7

• Manufacturer Part Number: AD9650
• Description: 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9650

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 105MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p,2.7 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, V
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
1
2
3
Conversion rate is the clock rate after the divider.
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
Wake-up time is defined as the time required to return to normal operation from power-down mode.
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty
CMOS Mode
LVDS Mode
CMOS Mode Pipeline Delay
LVDS Mode Pipeline Delay
Wake-Up Time
Out-of-Range Recovery
Mode (t
(Jitter, t
Data Propagation Delay
DCO Propagation Delay
DCO Propagation Delay
(Latency)
Time
DCO to Data Skew (t
Data Propagation Delay
DCO to Data Skew (t
DCS Enabled
DCS Disabled
Divide-by-1 Mode, DCS
Divide-by-1 Mode, DCS
Divide-by-2 Mode
(Latency) Channel A/
Channel B
Enabled
Disabled
Through Divide-by-8
Mode
(t
(t
(t
(t
PD
DCO
PD
DCO
)
)
J
)
)
CLK
)
2
2
)
3
1
A
)
SKEW
SKEW
CH
)
)
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
20
10
40
12
19
0.8
2.8
−0.6
2.9
−0.1
AD9650BCPZ-25
Typ
20
20
1.0
0.100
3.5
3.1
−0.4
3.7
3.9
+0.2
12
12/12.5
500
2
Max
200
25
25
28
21
4.2
0
4.5
+0.5
IN
= −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled,
Rev. A | Page 7 of 44
Min
20
10
15.4
4.65
7.33
0.8
2.8
−0.6
2.9
−0.1
AD9650BCPZ-65
Typ
7.70
7.70
1.0
0.090
3.5
3.1
−0.4
3.7
3.9
+0.2
12
12/12.5
500
2
Max
520
65
65
10.75
8.07
4.2
0
4.5
+0.5
Min
20
10
12.5
3.75
5.95
0.8
2.8
−0.6
2.9
−0.1
AD9650BCPZ-80
Typ
6.25
6.25
1.0
0.080
3.5
3.1
−0.4
3.7
3.9
+0.2
12
12/12.5
500
2
Max
640
80
80
8.75
6.55
4.2
0
4.5
+0.5
Min
20
10
9.5
2.85
4.5
0.8
2.8
−0.6
2.9
−0.1
AD9650BCPZ-105
Typ
4.75
4.75
1.0
0.075
3.5
3.1
−0.4
3.7
3.9
+0.2
12
12/12.5
500
2
Max
640
105
105
6.65
5.0
4.2
0
4.5
+0.5
AD9650
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
Cycles
Cycles
µs
Cycles